Bus Page Logic Enable, Bus Dram Page Size

Bus Interface Unit (BIU) Registers

Table 4-10.DRAM Control Register (DCR) Bit Definitions (Continued)

Bit	Bit Name	Reset	Description
Number	Bit Name	Value	Description
Number		Value



11	BPLE	0	Bus Page Logic Enable
			Enables/disables the in-page identifying logic. When BPLE is set, it enables the page
			logic (the page size is defined by BPS[1–0] bits). Each in-page identification causes the
			DRAM controller to drive only the column address (and the associated CAS signal).
			When BPLE is cleared, the page logic is disabled, and the DRAM controller always
			accesses the external DRAM in out-of-page accesses (for example, row address with
			RAS assertion and then column address with CAS assertion). This mode is useful for
			low power dissipation. Only one in-page identifying logic exists. Therefore, during
			switches from one DRAM external bank to another DRAM bank (the DRAM external
			banks are defined by the access type bits in the AARs, different external banks are
			accessed through different AA/RAS pins), a page fault occurs.

10		0	Reserved. Write to zero for future compatibility.
9–8	BPS[1–0]	0	Bus DRAM Page Size
			Defines the size of the external DRAM page and thus the number of the column
			address bits. The internal page mechanism works according to these bits only if the
			page logic is enabled (by the BPLE bit). The four combinations of BPS[1–0] enable the
			use of many DRAM sizes (1 M bit, 4 M bit, 16 M bit, and 64 M bit). The encoding of
			BPS[1–0] is:
			ν 00 = 9-bit column width, 512 words
			ν 01 = 10-bit column width, 1 K words
			ν 10 = 11-bit column width, 2 K words
			ν 11 = 12-bit column width, 4 K words
			When the row address is driven, all 24 bits of the external address bus are driven [for
			example, if BPS[1–0] = 01, when driving the row address, the 14 MSBs of the internal
			address (XAB, YAB, PAB, or DAB) are driven on address lines A[0–13], and the
			address lines A[14–23] are driven with the 10 MSBs of the internal address. This
			method enables the use of different DRAMs with the same page size.

7–4		0	Reserved. Write to zero for future compatibility.
3–2	BRW[1–0]	0	Bus Row Out-of-page Wait States
			Defines the number of wait states that should be inserted into each DRAM out-of-page
			access. The encoding of BRW[1–0] is:
			ν 00 = 4 wait states for each out-of-page access
			ν 01 = 8 wait states for each out-of-page access
			ν 10 = 11 wait states for each out-of-page access
			ν 11 = 15 wait states for each out-of-page access

1–0	BCW[1–0]	0	Bus Column In-Page Wait State
			Defines the number of wait states to insert for each DRAM in-page access. The
			encoding of BCW[1–0] is:
			ν 00 = 1 wait state for each in-page access
			ν 01 = 2 wait states for each in-page access
			ν 10 = 3 wait states for each in-page access
			ν 11 = 4 wait states for each in-page access

4-26	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 Bus Page Logic Enable, Bus Dram Page Size, Bus Row Out-of-page Wait States

Models: DSP56301

Table 4-10.DRAM Control Register (DCR) Bit Definitions (Continued)

Bus Page Logic Enable

Bus DRAM Page Size

Bus Row Out-of-page Wait States

Bus Column In-Page Wait State

DSP56301 specifications