SCI Initialization | Motorola DSP56301 specification

SCI Initialization

Table 8-1.SCI Registers After Reset (Continued)

Register		Bit Mnemonic	Bit Number		Reset Type

				HW Reset	SW Reset	IR Reset	ST Reset
				HW Reset	SW Reset	IR Reset	ST Reset


SSR		R8	7	0	0	0	0
		FE	6	0	0	0	0
		PE	5	0	0	0	0
		OR	4	0	0	0	0
		IDLE	3	0	0	0	0
		RDRF	2	0	0	0	0
		TDRE	1	1	1	1	1
		TRNE	0	1	1	1	1

		TCM	15	0	0	—	—
		RCM	14	0	0	—	—
SCCR		SCP	13	0	0	—	—
		COD	12	0	0	—	—
		CD[11–0]	11–0	0	0	—	—

SRX		SRX[23–0]	23–16, 15–8, 7–0	—	—	—	—

STX		STX[23–0]	23–0	—	—	—	—

SRSH		SRS[8–0]	8–0	—	—	—	—

STSH		STS[8–0]	8–0	—	—	—	–

SRSH	SCI receive shift register, STSH—SCI transmit shift register
HW	Hardware reset is caused by asserting the external RESET signal.
SW	Software reset is caused by executing the RESET instruction.
IR	Individual reset is caused by clearing PCRE (bits 0–2) (configured for GPIO).
ST	Stop reset is caused by executing the STOP instruction.
1	The bit is set during this reset.
0	The bit is cleared during this reset.
—	The bit is not changed during this reset.

8.4SCI Initialization

The SCI is initialized as follows:

1.Ensure that the SCI is in its individual reset state (PCRE = $0). Use a hardware RESET signal or software RESET instruction.

2.Program the SCI control registers.

3.Configure at least one SCI signal as an SCI signal.

If interrupts are to be used, the signals must be selected, and global interrupts must be enabled and unmasked before the SCI can operate. The order does not matter; any one of these three requirements for interrupts can enable the SCI, but the interrupts should be unmasked last (that is, I[1–0] bits in the Status Register (SR) should be changed last). Synchronous applications usually require exact frequencies, so the crystal frequency must be chosen carefully. An alternative to selecting the system clock to accommodate the SCI requirements is to provide an external clock to the SCI. When the SCI is configured in Synchronous mode, internal clock, and all the SCI pins are simultaneously enabled, an extra pulse of one DSP clock length is provided on the SCLK pin.

8-6	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual SCI Initialization

Models: DSP56301

Table 8-1.SCI Registers After Reset (Continued)

SRSH

8.4SCI Initialization

DSP56301 specifications