Timer Load Register TLR, Positive polarity

Triple Timer Module Programming Model

Table 9-4.Inverter (INV) Bit Operation (Continued)

	TIO Programmed as Input		TIO Programmed as Output
Mode
	INV = 0	INV = 1	INV = 0	INV = 1

4	Width of the high input	Width of the low input
	pulse is measured.	pulse is measured.	—	—

5	Period is measured between	Period is measured
	the rising edges of the input	between the falling edges
	signal.	of the input signal.	—	—
			—	—

6	Event is captured on the	Event is captured on the
	rising edge of the signal	falling edge of the signal
	from the TIO signal.	from the TIO signal.	—	—
			—	—

7			Pulse generated by	Pulse generated by the
	—	—	the timer has	timer has negative
			positive polarity.	polarity.

9			Pulse generated by	Pulse generated by the
	—	—	the timer has	timer has negative
			positive polarity.	polarity.

10			Pulse generated by	Pulse generated by the
	—	—	the timer has	timer has negative
			positive polarity.	polarity.

9.4.5Timer Load Register (TLR)

The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR value after the TCSR[TE] bit is set and a first event occurs.

νIn timer modes, if the TCSR[TRM] bit is set, the counter is reloaded each time after it reaches the value contained by the timer compare register and the new event occurs.

νIn measurement modes, if TCSR[TRM] and TCSR[TE] are set, the counter is reloaded with the value in the TLR on each appropriate edge of the input signal.

νIn PWM modes, if TCSR[TRM] is set, the counter is reloaded each time after it overflows and the new event occurs.

νIn watchdog modes, if TCSR[TRM] is set, the counter is reloaded each time after it reaches the value contained by the timer compare register and the new event occurs. In this mode, the counter is also reloaded whenever the TLR is written with a new value while TCSR[TE] is set.

νIn all modes, if TCSR[TRM] is cleared (TRM = 0), the counter operates as a free-running counter.

Triple Timer Module

9-33

DSP56301 specifications

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In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Timer Load Register TLR, Positive polarity

Models: DSP56301

Table 9-4.Inverter (INV) Bit Operation (Continued)

TIO Programmed as Input

Mode

positive polarity.

Pulse generated by

the timer has

timer has negative

9.4.5Timer Load Register (TLR)

Triple Timer Module

DSP56301 specifications