Motorola DSP56301 user manual DSP PCI Control Register Dpcr Address XFFFFC6 Read/Write

Programming Sheets

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Sheet 2 of 10

Host Processor (HI32)

Insert Address Enable, Bit 21

Clear Transmitter, Bit 14

0 = Does not write PCI transaction address.

0 = No data transaction pending.

1 = Clears HI32 master-to-host bus data path.

1 = Writes PCI transaction address to HTXR.

(Ignored when HI32 is not in PCI mode. Can be

set only when DPCR[RBLE]] = 1.)

Transfer Complete Interrupt Enable, Bit 12

0 = Disables transfer complete interrupt requests.

1 = Enables transfer complete interrupt requests.

Receive Buffer Lock Enable, Bit 20

0 = HDTC bit not set. PCI write access to HTXR

Transaction Termination Interrupt Enable, Bit 9

can occur.

1 = HDTC bit is set. PCI write access to HTXR

0 = Disables transaction interrupt requests.

1 = Enables transaction interrupt requests.

cannot occur.

Master Wait State Disable, Bit 19

Transaction Abort Interrupt Enable, Bit 7

0 = Enables insertion of PCI wait states.

0 = Disables transaction abort interrupts.

1 = Disables insertion of PCI wait states.

1 = Enables transaction abort interrupts.

Parity Error Interrupt Enable, Bit 5

Master Access Counter Enable, Bit 18

0 = Disables parity error interrupts.

0 = Disables master access counter.

1 = Enables parity error interrupts.

1 = Enables master access counter.

Master Address Interrupt Enable, Bit 4

System Error Force, Bit 16

0 = Disables master address interrupts.

0 = HI32 hardware controls the HSERR pin.

1 = Enables master address interrupts.

1 = Pulse HSERR pin one PCI clock cycle.

Master Receive Interrupt Enable, Bit 2

0 = Disables master receive interrupts.

Master Transfer Terminate, Bit 15

1 = Enables master receive interrupts.

0 = PCI bus is in idle state.

1 = Generates master-initiated

Master Transmit Interrupt Enable, Bit 1

transaction termination

0 = Disables master transmit interrupts.

1 = Enables master transmit interrupts.

23		22	21	20		19	18	17	16		15	14	13	12	11 10		9	8	7	6	5	4	3	2	1	0
	*0	*0	IAE	RBLE	MWSD		MACE	*0	SERF	MTT		CLRT	*0	TCIE	*0	*0	TTIE	*0	TAIE	*0	PEIE	MAIE	*0	MRIE	MTIE	*0
	DSP PCI Control Register (DPCR)										Address: X:FFFFC6 Read/Write
	Reset = $000000																			*	= Reserved, Program as 0
	Note: All bits work only in PCI mode (DCTR[HM] = $1).

Figure B-11.DSP PCI Control Register (DPCR)

Programming Reference B-23