Index-6 DSP56301 User’s Manual | Motorola specification

General-Purpose Input/Output (GPIO) 1-5,1-6,2-2,5-4data register 6-43

direction register 6-43ESSI0 5-6

ESSI1 5-6

HI08 5-5

Port B 2-3,5-5Port C 5-6Port D 5-6Port E 5-6SCI 5-6timer 5-7

GPIO mode 6-13ground (GND) 2-1,2-4

handshake flags 6-44hardware stack 1-8

Header Type (HT[7–0]) bits 6-68

Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)

Cache Line Size (CLS[7–0]) 6-69Latency Timer (High) (LT[7–0]) 6-69

HI32 Active (HACT) bit 6-35HI32 Control Register (HCTR)

DMA Enable (DMAE) 6-54Host Flags 2–0 (HF[2–0]) 6-54

Host Receive Data Transfer Format (HRF[1–0]) 6-50Host Semaphores (HS[2–0]) 6-49

Host Transmit Data Transfer Format (HTF[1–0]) 6-51

Receive Request Enable (RREQ) 6-55Slave Fetch Type (SFT) 6-52

Target Wait State Disable (TWSD) 6-49

Transmit Request Enable (TREQ) 6-56HI32 Interrupt Priority Level (HPL) bits 4-16HIRQ pin 6-69

Host Command (HC) bit 6-61

Host Command Interrupt Enable (HCIE) bit 6-26Host Command Pending (HCP) bit 6-37

Host Command Vector (HV[6–0]) bits 6-60Host Command Vector Register (HCVR) 6-59

Host Command (HC) 6-61

Host Command Vector (HV[6–0]) 6-60Host Non-Maskable Interrupt (HNMI) 6-60

Host Data Direction Register (HDDR) programming sheet B-40

Host Data Register (HDR) programming sheet B-40

Host Data Strobe Mode (HDSM) bit 6-25Host DMA Request Polarity (HDRP) bit 6-24

Host Flags 2–0 (HF[2–0]) bits	6-36,6-54
Host Flags 5–3 (HF[5–3]) bits	6-26,6-57

Host Interface (HI32) 1-5,2-2

16-bit data Universal Bus mode 6-48active PCI master 6-13

address insertion 6-4

bit manipulation instructions 6-26block diagram 6-5

byte enable pins 6-45

Cache Line Size Configuration Register (CCLS) 6-34Class Code/Revision ID Configuration Register

(CCCR/CRID) 6-67

PCI Device Base Class (BC[7–0]) 6-67

PCI Device Program Interface (P[17–10]) 6-67PCI Device Sub-Class (SC[7–0]) 6-67Revision ID (RID[7–0]) 6-67

clearing the HM bits 6-13Configuration space accesses 6-45core interrupts 6-4

data transfer 6-6

data transfer format converter 6-63deadlock 6-46

Device/Vendor ID Configuration Register (CDID/CVID) 6-64

disable PCI wait states 6-28DMA 6-22

DMA transfers 6-42

DSP Control Register (DCTR) 6-23

Host Command Interrupt Enable (HCIE) 6-26Host Data Strobe Mode (HDSM) 6-25

Host DMA Request Polarity (HDRP) 6-24Host Flags 5–3 ‹HF[5–3]) 6-26

Host Interrupt A (HINT) 6-25

Host Interrupt Request Drive Control (HIRD) 6-24

Host Interrupt Request Handshake Mode (HIRH) 6-24

Host Read/Write Polarity (HRWP) 6-25Host Reset Polarity (HRSP) 6-24Host Transfer Acknowledge Polarity

(HTAP) 6-25

Slave Receive Interrupt Enable (SRIE) 6-26Slave Transmit Interrupt Enable (STIE) 6-26DSP Host Port GPIO Data Register (DATH) 6-43

DSP Host Port GPIO Direction Register (DIRH) 6-43DSP Master Transmit Data Register (DTXM) 6-42DSP PCI Address Register (DPAR) 6-33

DSP PCI Transaction Address (Low) (AR[15–0] 6-34

PCI Bus Command (C[3–0]) 6-34

PCI Byte Enables (BE[3–0] ) 6-33

DSP PCI Master Control Register (DPMC) 6-30Data Transfer Format Control (FC[1–0]) 6-31

Index-6

DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola user manual Index-6 DSP56301 User’s Manual

Models: DSP56301

Index-6

DSP56301 User’s Manual

DSP56301 specifications