DMA Control Registers 5-0 DCR5-0, Dcon | Motorola DSP56301 specs

DMA Control Registers 5–0 (DCR[5–0])

Table 4-11.Address Attribute Registers (AAR[0–3]) Bit Definitions (Continued)

Bit	Bit Name	Reset		Description
Number	Bit Name	Value		Description
Number		Value


1–0	BAT[1–0]	0	Bus Access Type
			Read/write bits that define the type of external memory (DRAM or SRAM) to access for
			the area defined by the BAC[11–0],BYEN, BXEN, and BPEN bits. The encoding of
			BAT[1–0] is:
			ν 00	= Reserved
			ν 01	= SRAM access
			ν 10	= DRAM access
			ν 11	= Reserved

			When the external access type is defined as a DRAM access (BAT[1–0] = 10), AA/RAS
			acts as a Row Address Strobe (RAS) signal. Otherwise, it acts as an Address Attribute
			signal. External accesses to the default area always execute as if BAT[1–0] = 01 (that is,
			SRAM access). If Port A is used for external accesses, the BAT bits in the AAR3–0
			registers must be initialized to the SRAM access type (that is, BAT = 01) or to the DRAM
			access type (that is BAT = 10). To ensure proper operation of Port A, this initialization
			must occur even for an AAR register that is not used during any Port A access.
			Note: At reset, the BAT bits are initialized to 00.

4.7DMA Control Registers 5–0 (DCR[5–0])

The DMA Control Registers (DCR[5–0]) are read/write registers that control the DMA operation for each of their respective channels. All DCR bits are cleared during processor reset.

DIE

DTM2

DTM1

DTM0

DPR1

DPR0

DCON

DRS4

DRS3

DRS2

DRS1

DRS0

D3D

DAM5

DAM4

DAM3

DAM2

DAM1

DAM0

DDS1

DDS0

DSS1

DSS0

Figure 4-9.DMA Control Register (DCR)

Table 4-12.DMA Control Register (DCR) Bit Definitions

Bit

Bit Name

Reset

Description

Number

Value

DMA Channel Enable

Enables the channel operation. Setting DE either triggers a single block DMA transfer in the

DMA transfer mode that uses DE as a trigger or enables a single-block, single-line, or

single-word DMA transfer in the transfer modes that use a requesting device as a trigger. DE

is cleared by the end of DMA transfer in some of the transfer modes defined by the DTM bits.

If software explicitly clears DE during a DMA operation, the channel operation stops only

after the current DMA transfer completes (that is, the current word is stored into the

destination).

Core Configuration

4-29

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual DMA Control Registers 5-0 DCR5-0, DIE DTM2 DTM1 DTM0, Dcon

Models: DSP56301

Bus Access Type