LOOP0 | Motorola DSP56301 guide

bra

<UB1HOSTLD

; MD:MC:MB:MA=1111, UB single strobe

;========================================================================

;This is the routine that loads from the Host Interface in UB (UNIVERSAL) mode,

;with single-strob pin configuration (RD/WR,DS).

;MD:MC:MB:MA=x111 - Host UB

UB1HOSTLD
bset #13,x1	; HDSM=1 (Double-strob pin mode disabled)

;========================================================================

;This is the routine that loads from the Host Interface in UB (UNIVERSAL) mode,

;with double-strobe pin configuration (RD,WR).

;MD:MC:MB:MA=x110 - Host UB

UB2HOSTLD

movep x1,X:M_DCTR do #6,_LOOP0 jclr #2,X:M_DSR,* movep X:M_DRXR,a2 asr #8,a,a

_LOOP0

move a1,r0 move a1,r1

; Download P memory through UB

do a0,_LOOP1 do #3,_LOOP2

_LBLA

jset #2,X:M_DSR,_LBLB jclr #3,X:M_DSR,_LBLA enddo

bra <TERMINATE

_LBLB

movep X:M_DRXR,a2 asr #8,a,a

_LOOP2

movem a1,p:(r0)+ nop

_LOOP1

bra <FINISH

;Configure HI32 in UB mode Single or Double strobe

;read # of words and start address

;Wait for SRRQ to go high (i.e. data ready)

;

;Shift 8 bit data into A1

;starting address for load

;save it in r1

;a0 holds the number of words

;Load instruction words

;for each byte

;Wait for SRRQ to go high (i.e. data ready)

;If HF0=1, stop loading new data.

;Must terminate the do loop

;Terminate loop (enddo) and finish

;Store 16-bit data in accumulator

;Shift 8 bit data into A1

;and go get another 24-bit word.

;Store 24-bit data in P mem

;movem cannot be at LA.

;and go get another 24-bit word.

;finish bootstrap

;======================================================================== ; This routine loads from the Host Interface in ISA (UNIVERSAL) mode.

; MD:MC:MB:MA=x101 - Host ISA

; 16-bit wide dual-strobe Universal Bus mode (e.g to support ; ISA (slave) glue less connection).

; Using self configuration mode, the base address in CBMA is written with ; $2f which corresponds to an ISA HTXR address of $2fe (Serial Port 2 Modem

; Status read only register).
ISAHOSTLD
move #$5a,b	; b1=$5a0000
movep b1,X:M_DCTR	; Configure HI32 as Self-Config
movep #$00002f,X:M_DPMC ; write to DPMC
rep #4
movep X0,X:M_DPAR	; write to DPAR (CSTR+CCMR,CCCR+CRID,CLAT,CBMA)
	; completing 32 bit write

A-8	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual LOOP0

Models: DSP56301

_LOOP0

_LOOP1

DSP56301 User’s Manual

DSP56301 specifications