Hbs, Hpar, Hdak, Hperr, Hdrq, Hgnt, Haen, Hreq

Host Interface (HI32)

Table 2-10.Host Interface (Continued)

Signal Name	Type	State During	Signal Description
Signal Name	Type	Reset	Signal Description
		Reset


	Input/	Tri-stated	Host Lock—When the HI32 is programmed to interface with a PCI
HLOCK	Input/	Tri-stated
	Output		bus and the HI function is selected, this is the Host Lock signal.
	Input		Host Bus Strobe—When HI32 is programmed to interface with a
HBS	Input		Host Bus Strobe—When HI32 is programmed to interface with a
			universal non-PCI bus and the HI function is selected, this signal is
			Host Bus Strobe Schmitt-trigger input.
PB23	Input or		Port B 23—When the HI32 is configured as GPIO through the
	Output		DCTR, this signal is individually programmed as an input or output
			through the HI32 DIRH.

HPAR	Input/	Tri-stated	Host Parity—When the HI32 is programmed to interface with a PCI
	Output		bus and the HI function is selected, this is the Host Parity signal.
	Input		Host DMA Acknowledge—When HI32 is programmed to interface
HDAK	Input		Host DMA Acknowledge—When HI32 is programmed to interface
			with a universal non-PCI bus and the HI function is selected, this
			signal is Host DMA Acknowledge Schmitt-trigger input.
			Port B —When the HI32 is configured as GPIO through the DCTR,
			this signal is internally disconnected.

	Input/	Tri-stated	Host Parity Error—When the HI32 is programmed to interface with
HPERR	Input/	Tri-stated
	Output		a PCI bus and the HI function is selected, this is the Host Parity
			Error signal.
HDRQ	Output		Host DMA Request—When HI32 is programmed to interface a with
			universal non-PCI bus and the HI function is selected, this signal is
			Host DMA Request output.
			Port B —When the HI32 is configured as GPIO through the DCTR,
			this signal is internally disconnected.

	Input	Input	Host Bus Grant—When the HI32 is programmed to interface with a
HGNT	Input	Input
			PCI bus and the HI function is selected, this is the Host Bus Grant
			signal.
HAEN	Input		Host Address Enable—When HI32 is programmed to interface
			with a universal non-PCI bus and the HI function is selected, this
			signal is Host Address Enable output.
			Port B —When the HI32 is configured as GPIO through the DCTR,
			this signal is internally disconnected.

	Output	Tri-stated	Host Bus Request—When the HI32 is programmed to interface a
HREQ	Output	Tri-stated	Host Bus Request—When the HI32 is programmed to interface a
			PCI bus and the HI function is selected, this is the Host Bus Request
			signal.
HTA	Output		Host Transfer Acknowledge—When HI32 is programmed to
			interface with a universal non-PCI bus and the HI function is
			selected, this signal is Host Data Bus Enable output.
			Port B —When the HI32 is configured as GPIO through the DCTR,
			this signal is internally disconnected.

2-12	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Hbs, Hpar, Hdak, Hperr, Hdrq, Hgnt, Haen, Hreq, Hta

Models: DSP56301

Table 2-10.Host Interface (Continued)

Signal Name

HBS

HPAR

HDAK

HPERR

HDRQ

HGNT

HAEN

HREQ

HTA

DSP56301 specifications