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Motorola DSP56301 Timer Prescaler Count Register Tpcr, Timer Control/Status Register Tcsr

Models: DSP56301

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Triple Timer Module Programming Model

9.4.3Timer Prescaler Count Register (TPCR)

The TPCR is a read-only register that reflects the current value in the prescaler counter.

PC20

PC19

PC18

PC17

PC16

PC15

PC14

PC13

PC12

PC11

PC10

PC9

PC8

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

Reserved bit; read as 0; write to 0 for future compatibility

Figure 9-22.Timer Prescaler Count Register (TPCR)

Table 9-2.Timer Prescaler Count Register (TPCR) Bit Definitions

Bit Number	Bit Name	Reset Value	Description


23–21		0	Reserved. Write to zero for future compatibility.

20–0	PC[20–0]	0	Prescaler Counter Value
			Contain the current value of the prescaler counter.

9.4.4Timer Control/Status Register (TCSR)

The TCSR is a read/write register controlling the timer and reflecting its status.

23	22	21	20	19	18	17	16	15	14	13	12

		TCF	TOF					PCE		DO	DI
11	10	9	8	7	6	5	4	3	2	1	0

DIR		TRM	INV	TC3	TC2	TC1	TC0		TCIE	TOIE	TE

Reserved. Read as 0. Write to 0 for future compatibility

Figure 9-23.Timer Control/Status Register (TCSR)

Table 9-3.Timer Control/Status Register (TCSR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

23–22

Reserved. Write to zero for future compatibility.

9-28	DSP56301 User’s Manual

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Motorola DSP56301 Timer Prescaler Count Register Tpcr, Timer Control/Status Register Tcsr, Tcf Tof Pce, Trm Inv, Tcie Toie

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Contents

DSP56301 User’s Manual Revision 3, March Japan How to reach usUSA/EUROPE ASIA/PACIFICPage Page Contents Chapter Memory Configuration Chapter Core Configuration Chapter Programming the Peripherals Chapter Host Interface HI32 Chapter Enhanced Synchronous Serial Interface Essi Chapter Serial Communication Interface SCI Index Chapter Triple Timer ModuleChapter a Bootstrap Program Chapter B Programming Reference Figures DSP56301 User’s Manual Xii Pulse Width Modulation Toggle Mode, TRM = DSP Control Register Dctr DSP PCI Control Register Dpcr Tables Tables Essi Clock Sources Manual Organization Overview Manual Conventions High True/Low True Signal ConventionsSignal/Symbol Logic State Signal State Voltage Ground2 Ground PIN is a generic term for any pin on the chip DSP56300 Core Features Size Cache Program RAM Instruction Data RAM Switch Size Cache SizeCE = MS = DSP56300 Core Functional Blocks Data ALU Multiplier-Accumulator MAC Address Generation Unit AGUData ALU Registers Program Control Unit PCU PLL and Clock Oscillator Jtag TAP and OnCE Module On-Chip Memory DSP56301 Switch Memory ConfigurationInternal Buses Expansion Area DMAMemory Expansion Area Host Interface HI32 General-Purpose Input/Output Gpio signalsPeripherals Enhance Synchronous Serial Interface Essi Triple Timer Module Serial Communications Interface SCI Name Description Order Number Related Documents and Web SitesDSP56301 Documentation DSP56300FM/AD Enhanced Synchronous Serial Interfaces ESSI0 DSP56301 Functional Signal GroupingsTimers JTAG/OnCE Port ESSI1 Port a See -2for a listing of the Host Interface/Port B SignalsDSP56301 Host Interface/Port B Detail Signal Diagram Ground Signals PowerPower Inputs Ground Clock Clock SignalsPhase-Lock Loop Signals PLL External Data Bus External Memory Expansion Port Port aExternal Address Bus External Bus Control Output Tri-stated Is an active-low output that is Signals are tri-statedArbitration is reset to the bus slave state Output Tri-stated Is asserted for half a clock CAS Bclk Signal State Type During Signal Description Name Interrupt and Mode ControlInterrupt and Mode Control Nonmaskable Interrupt-After Host Interface HI32 10.Host Interface Command 0-3/Byte Enable 0-3 -When the HI32 is programmed Hdak HBSHpar Hperr Hstop HserrHirq HWR 11.Summary of HI32 Signals and Modes Signal PCI Mode Enhanced Universal Bus Mode Gpio Mode Name HAD11 HD3 HIO11 HP8 HAD8 HD0 HIO8 HP9 HAD9 HD1 HIO9HAD10 HD2 HIO10 HAD12 HD4 HIO12 Gpio 12.Host Port Pins HI32PCI Reserved Bus Command/Byte Enable Host Address BusHost Target Ready Host Data Bus Enable Host Initiator Ready Host Data Bus Direction Host Device Select Host Select Acknowledge Parity Error DMA RequestBus Grant Host Address Enable Host Lock Bus Strobe Hreq is deasserted in the same PCI Host System Error Host Interrupt RequestBus Request Host Transfer Acknowledge Hstr HRD/HDS Hstop HWR/HRWHost Stop Host Write/Read-Write Initialization Device Select Host Read/Data Strobe Host Bus Clock Address/Data Multiplexed Bus Data Bus Host Interrupt a Hardware ResetEnhanced Synchronous Serial Interface Active low, open drain output pin PC1 13.Enhanced Synchronous Serial InterfacePC0 PC2 SRD0 SCK0PC3 PC4 PD1 14.Enhanced Serial Synchronous InterfacePD0 PD2 SRD1 SCK1PD3 PD4 15.Serial Communication Interface TimersSerial Communications Interface SCI Timer 1 Schmitt-Trigger Input/Output- When Timer 16.Triple Timer SignalsTimer 0 Schmitt-Trigger Input/Output- When Timer Timer 2 Schmitt-Trigger Input/Output- When timer 17.JTAG/OnCE Interface Signal Name Type State During Signal Description ResetJtag and OnCE Interface Jtag and OnCE Interface DSP56301 User’s Manual Memory Configuration Program Memory Space Instruction Cache Memory Switch Modes-Program MemoryInternal Program Memory Memory Configuration Program Bootstrap ROMMemory Switch Modes-X Data Memory Data Memory Space Internal Y Data Memory Memory Switch Modes-Y Data MemoryInternal I/O Space-X Data Memory Dynamic Memory Configuration Switching External I/O Space-Y Data Memory DSP56301 RAM Configurations Sixteen-Bit Compatibility Mode ConfigurationInternal Memory Configuration Summary DSP56301 RAM Address Ranges by Configuration RAM DefaultMemory Maps 16-Bit Space With Default RAM 0, 0 None 64K $000-$FFF $000-$7FF 16M $000-$800 $000-$BFF 16-Bit Space With Switched Program RAM 0, 1 None 64K $000-$7FF $000-$BFF Instruction Cache Enabled 1, 0 $000-$BFF $000-$7FF Not addressable 16-Bit Space With Instruction Cache Enabled 1, 0 Addressable $000-$3FF $000-$BFF Not addressable $0400 $0000 Core Configuration Core Configuration DSP56301 Operating Modes Reset Description VectorOperating Modes Mode Operating Mode Definitions Mode Description DSP Clkout rate must be 5/3 of the PCI clock Address attributes selected defaultLow. The DSP56301 is written with 24-bit-wide words Bootstrap Program Central Processor Unit CPU Registers Status Register SR DMA OMR Do Forever Flag Cache EnableSixteen-Bit Arithmetic Mode Do Loop Flag Sixteen-Bit Compatibility Mode Interrupt Mask Scaling ModeScaling Rounding Bit SEquation Mode Priority Exceptions Exceptions Masked Permitted Extension Bit Number Bit Name Reset Value Description LimitScaling Mode Integer Portion Unnormalized Stack Extension Enable Operating Mode Register OMROperating Mode Register OMR Bit Definitions Stack Extension Wrap Flag Asynchronous Bus Arbitration Enable Address Trace EnableAddress Attribute Priority Disable Stack Extension Overflow Flag Bus Release Timing Cache Burst Mode EnableMemory Switch Mode Synchronize Select External Bus Disable Configuring InterruptsBit Number Bit Name Reset Value Description Stop Delay Mode Chip Operating Mode Interrupt Priority Registers Iprc and Iprp Interrupt Sources Interrupt Table Memory MapInterrupt Priority Level Bits VBA$1E VBA$1AVBA$1C VBA$2A Priority Interrupt Source Processing Interrupt Source Priorities Within an IPLInterrupt Source Priorities Within an IPL TIMER0 compare interrupt Host command interruptTIMER0 overflow interrupt TIMER1 overflow interrupt PLL Control Register Pctl PLL Control Register Pctl Bit Definitions Bus Interface Unit BIU Registers Bus Control Register Bus Area 2 Wait State Control Bus Default Area Wait State ControlBus Area 3 Wait State Control Bus Area 1 Wait State Control BRF3 BRF2 BRF1 Dram Control Register DCRBRP BRF7 BRF6 Bstr Bren BME Bple BPS1 10.DRAM Control Register DCR Bit Definitions Bus Row Out-of-page Wait States Bus Page Logic EnableBus Dram Page Size Bus Column In-Page Wait State Bus Number of Address Bits to Compare Address Attribute Registers AAR0-3Bus Address to Compare Bus X Data Memory Enable Bus Packing EnableBus Y Data Memory Enable Bus Program Memory Enable Dcon DMA Control Registers 5-0 DCR5-0DIE DTM2 DTM1 DTM0 DAM5 DAM4 DAM3 DAM2 DAM1 DAM0 DTM2-0 Trigger Cleared Transfer Mode After DMA Interrupt EnableDMA Transfer Mode 12.DMA Control Register DCR Bit Definitions DMA address generation logic, buses, and so forth Number ValueDMA Channel Priority DPR1-0 Channel Priority Dcon DMA Continuous Mode EnableOMR CDP1-0 CP1-0 Core Priority DRS4-0 Requesting Device Three-Dimensional ModeDMA Request Source DSS1 DSS0 Device Identification Register IDRDDS1 DDS0 Version Information Design Center Jtag Identification ID RegisterJtag Boundary Scan Register BSR Number Identity See Note Jtag Boundary Scan Register BSR DSP56301 User’s Manual Peripheral Initialization Steps Programming the Peripherals Polling Mapping the Control RegistersData Transfer Methods Data Memory Interrupts Advantages and Disadvantages General-Purpose Input/Output Gpio3 DMA Port B Signals and Registers Port E Signals and Registers Port C Signals and RegistersPort D Signals and Registers Triple Timer Signals and Registers Timer Gpio General-Purpose Input/Output Gpio DSP56301 User’s Manual Features Host Interface HI32 HI32 Features, Core-Side and Host-Side HI32 Features in PCI Mode and Universal Bus Mode Overview DSP DMA Data Bus DSP Global Data Bus PCI Configuration SpaceDSP-Side Registers Data transfer format converter Data Transfer Paths Host-to-DSP Data Path DSP-To-Host Data Path FC1 FC0 HI32 PCI Master Data Transfer FormatsDpmc Two least significant bytes of two Hrxm HTF1 HTF0 Transmit Data Transfer FormatHctr HRF Receive Transfer Data FormatsDSP to Host Data Transfer Format Three least significant Hrxs bytes Receive Transfer Data Formats DSP-Side Operating Modes Reset StatesType Entered when Description HRST/HRST HI32 Mode Terminate and Reset Dctrhm = $0PCI Mode Dctrhm = $1 PCI Example 6-1. PCI /DMA Throughput 32-Bit Multfactor Gpio Mode Dctrhm = $4 Self-Configuration Mode Dctrhm = $5 Example 6-3. Self-Configuration Procedure for PCI Mode Host Port Pin Functionality Host Port PinsPCI Bus Universal Bus Mode DSP56301 ISA Master Slave HI32 Programming Model, DSP Side Memory Register Address ModeHI32 DSP-Side Programming Model Bit Number Bit Name Mode Description ValueDSP Control Register Dctr 10.DSP Control Register Dctr Bit Definitions Host Transfer Acknowledge Polarity Host Data Strobe ModeHtap Host Read/Write Polarity Host Command Interrupt Enable Slave Receive Interrupt EnableSlave Transmit Interrupt Enable DSP PCI Control Register Dpcr 11.DSP PCI Control Register Dpcr Bit Definitions Insert Address EnableReceive Buffer Lock Enable IAE Force Master Wait State DisableMaster Access Counter Enable Hserr Transaction Abort Interrupt Enable Transfer Complete Interrupt EnableTransaction Termination Interrupt Enable Parity Error Interrupt Enable BL1 BL0 DSP PCI Master Control Register DpmcBL4 A PCI DSP-to-Host transaction 12.DSP PCI Master Control Register Dmpc Bit DefinitionsData Transfer Format Control A PCI Host-to-DSP transaction PCI Data Burst Length DSP PCI Transaction Address High BE2 BE1 DSP PCI Address Register Dpar13.DSP PCI Address Register Dpar Bit Definitions AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 DSP PCI Transaction Address Low PCI Bus CommandC3-0 Command Type AR1 AR0 14.DSP Status Register DSR Bit Definitions Bit Bit Name Reset Mode Description Number ValueDSP Status Register DSR 2322212019181716 Srrq UBM Slave Receive Data Request 14. DSP Status Register DSR Bit Definitions Mode Description Number ValueHost Command Pending Slave Transmit Data Request Rdcq MDT Hdtc Trty Tdis TAB MAB DSP PCI Status Register Dpsr15.DSP PCI Status Register Dpsr Bit Definitions Aper Marq Mrrq Mtrq MWS PCI Time Out Termination Master Data TransferredPCI Host Data Transfer Complete PCI Target Retry PCI Target Disconnect PCI Data Parity ErrorPCI Address Parity Error PCI Target Abort PCI Master Wait States DSP Receive Data Fifo Drxr15. DSP PCI Status Register Dpsr Bit Definitions PCI Master Receive Data Request DSP Master Transmit Data Register Dtxm DSP Slave Transmit Data Register Dtxs 16.DATH and Dirh Functionality DSP Host Port Gpio Direction Register DirhDSP Host Port Gpio Data Register Dath Memory Register Host-Side Programming Model17.HI32 Programming Model, Host-Side Registers Host-Side Programming Model HC3/HBE3-HC0/HBE0 18.PCI Bus CommandsExecuted as Command Type Ignored 19. Host-Side Registers PCI Memory Address Space 20. Host-Side Registers PCI Configuration Address Space21. Host-Side Registers Universal Bus Mode Address Space 1 HI32 Control Register Hctr 13.Host Interface Control Register Hctr 22.Host Interface Control Register Hctr Bit Definitions Bit Bit Name Reset Mode Description NumberTarget Wait State Disable Twsd PCI Host Receive Data Transfer Format Host Transmit Data Transfer Format Slave Fetch Type Inserted AddressSFT UBM Reset, and Strq and Hstrhrrq are cleared Universal Bus mode Fetch SFT =Cleared when the DSP56300 core writes to Data path is lost when the reset state is Hirq Dmae UBMDmae Haen Dmae Treq Rreq Receive Req uest EnableRreq UBM Hirq Pin Hdrq pin Trdy Host Interface Status Register HstrHreq Hint HF5 HF4 HF3 UBM UBM UBM UBM UBM UBM PCI PCI PCI PCI PCI PCI Host interrupt a 23.Host Interface Status Register Hstr Bit DefinitionsHost Request Treq Rreq Hreq Transmitter Ready Host Receive Data RequestHost Transmit Data Request Host Command Vector Register Hcvr 15.Host Command Vector Register Hcvr Bit Bit Name Reset Value Mode Description Number 24.Host Command Vector Register Hcvr Bit DefinitionsHost Command Vector Hnmi UBM Host Master Receive Data Register Hrxm Host CommandWhen the DSP56300 core acknowledges the host command Host Slave Receive Data Register Hrxs Host Transmit Data Register Htxr PCI Mode Dctrhm = $1 Universal Bus mode Dctrhm = $2 or $3 DPE SSE RMA RTA STA Device ID/Vendor ID Configuration Register CDID/CVIDStatus/Command Configuration Register CSTR/CCMR DPR Fbbc Signalled Target Abort Detected Parity ErrorSignaled System Error Received Master Abort Parity Error Response System Error EnableWait Cycle Control hardwired to zero Bus Master Enable Class Code/Revision ID Configuration Register CCCR/CRID HT7-0 Header Type hardwired to $00HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0 Read-only bits that identify the layout of bytes $10-$3F Ccls Latency Timer HighCache Line Size PM8 PM7 PM6 PM5 PM4 MS1 MS0 MSI Memory Space Base Address Configuration Register CbmaUniversal Bus Mode Base Address Memory Base Address High/Low Pre-Fetch Hardwired to zero 29. Memory Space Base Address Configuration Register CbmaMemory Base Address Low Hardwired to zeros Memory Space Hardwired to zeros Example 6-5. Code for Setting the Csid IL1 IL0 Interrupt Line-Interrupt Pin Configuration RegisterCILPIL5 IL4 Maxlat Dctr Hcie HI32 Programming Model/Quick ReferenceHS PH PS UBM Hrsp Rble Dpcr MtieClrt DSR HCP DpmcDpar Hact Hdtc Dpsr AperDper Rdcq ISA/EISA TreqDmae SFT Hrxm HcvrHnmi Hrxs Chty Ccmr RMACccr Cbma MSI Tsmb TX0 CRA GDB DDB RclkRsma Rsmb Tsma Tclk STD SC0 Essi Enhancements Serial Receive Data Signal SRD Essi Data and Control SignalsSerial Transmit Data Signal STD Serial Clock SCK Serial Control Signal SC0 Serial Control Signal SC1 SYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD Mode and Signal DefinitionsControl Bits Essi Signals Operation Serial Control Signal SC2Essi After Reset Initialization Exceptions Operation Write data to all enabled transmit registers Normal/Network/On-Demand Mode Selection Operating Modes Normal, Network, and On-Demand Frame Sync Selection Frame Sync Signal FormatSynchronous/Asynchronous Operating Modes Frame Sync Polarity Frame Sync Length for Multiple DevicesWord Length Frame Sync and Data Word Timing Byte Format LSB/MSB for the Transmitter Flags WL2 WL1 WL0 ALC Essi Programming ModelEssi Control Register a CRA PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Word Length Control Essi Control Register a CRA Bit DefinitionsSelect SC1 Essi Word Length Selection Prescaler Range Alignment ControlFrame Rate Divider Control Prescale Modulus Select Rclock CRBTE1 CRBOF0 SSISRIF0Crbsyn = Tclock OF1 OF0 Essi Control Register B CRBShfd ESSI0 X$FFFFB6, ESSI1 X$FFFFA6 Essi Control Register B CRB Bit Definitions Transmit 0 Enable Transmit Interrupt EnableReceive Enable TIE Mode Select Transmit 1 EnableTransmit 2 Enable Synchronous/Asynchronous FSL1 FSL0 Serial Output Flag Serial Control DirectionOF1 OF0 TX Frame Sync TX Serial Data Serial Clock RX, TX Frame Sync RX, TX Serial DataSerial Clock RX Frame Sync RX Serial Data CRB SYN Bit Operation Essi Bit Receiver Interrupt or DMA Request and Flags Set Bit OperationSSI Control Register B CRB READ/WRITE Frame Sync FSL0 = 0, FSL1 = Data Out Flags Frame Sync FSL0 = 0, FSL1 = Data Flags Essi Status Register Ssisr Receiver Overrun Error FlagTransmitter Underrun Error Flag Receive Data Register Full Transmit Frame Sync Flag Essi Receive Shift RegisterReceive Frame Sync Flag Serial Input Flag Essi Receive Data Register RX Essi Transmit Shift Registers Receive Registers Transmit Registers Least Significant Transmit Middle Byte Transmit Low Byte Register 24 BitWL0 MSB Transmit Slot Mask Registers TSMA, Tsmb Essi Transmit Data Registers TX2-0Essi Time Slot Register TSR TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 15.ESSI Transmit Slot Mask Register B Tsmb RS1 RS0 Receive Slot Mask Registers RSMA, RsmbRS7 RS6 RS15 RS14 RS13 RS12 RS11 RS10 Gpio Signals and Registers Port Control Registers Pcrc and Pcrd ESSI0/ESSI1 Essi Port Signal ConfigurationsPort Direction Registers Prrc and Prrd Port Data Registers Pdrc and Pdrd 20.Port Data Registers Pdrc X$FFFFBD Pdrd X $FFFFAD Serial Communication Interface SCI Serial Communication Interface SCI Multidrop Mode Synchronous ModeAsynchronous Mode Address Mode Wakeup I/O SignalsWired-OR Mode Transmitting Data and Address Characters SCI Serial Clock Sclk Receive Data RXDTransmit Data TXD Reie Sckp Stir Tmie TIE RIE Ilie SCI After ResetSCI Registers After Reset Woms RWU Wake SBK Ssftd SCI Initialization Preamble, Break, and Data Transmission Priority Bootstrap Loading Through the SCI Boot Mode 2 or a Exceptions SCI Programming Model Bit Asynchronous 1 Start, 8 Data, 1 Stop Bit Synchronous Data Shift Register ModeWDS2 WDS1 WDS0 Bit Asynchronous 1 Start, 8 Data, 1 Even Parity, 1 Stop SCI Data Word Formats Ssftd = 0 Stir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2 SCI Control Register SCRReie SCI Receive Interrupt Enable Timer Interrupt EnableSCI Transmit Interrupt Enable Idle Line Interrupt Enable Woms Receiver EnableWired-OR Mode Select Send Break Receiver Wakeup EnableWakeup Mode Select SCI Shift Direction WDS1 WDS0 Mode Word FormatsWord Select Idle Rdrf Tdre Trne SCI Status Register SSRSCI Status Register SCI Status Register SSR Bit Definitions Transmitter Empty Idle Line FlagTdre TCM RCM SCI Clock Control Register SccrTCM RCM SCP COD Sclk CD11-0 Bit CounterDivide by Sckp = 0 + Sckp = RX, TX Data Ssftd = X1 Clock X16 Clock Sckp = SCI Receive Data Shift Register SCI Data RegistersSCI Receive Register SRX SCI Transmit Register STX Sclk TXD RXD Port E Control Register PcrePE2 PE1 PE0 PRRE1 PRRE0 Port E Direction Register PrrePort E Data Register Pdre PDRE1 PDRE0 Gpio Signals and Registers DSP56301 User’s Manual Triple Timer Module Triple Timer Module GDB Triple Timer Module Block DiagramIndividual Timer Block Diagram Tpcr Timer After Reset Timer Module Block Diagram Timer Initialization Timer Exceptions TCSR0 Tcie TC3 TC2 TC1 TC0 Triple Timer ModesTimer Gpio Mode TIO TCR Tcpr Mode 0 internal clock, no timer output TRM =TLR Output Timer Pulse ModeMode 1 internal clock TRM = Pulse width = timer clock Period Toggle Timer Timer Toggle ModeMode 2 internal clock TRM = 1 first event = write preload = write compare Clock CLK/2 or prescale CLK = write compare Clock CLK/2 or prescale CLK Mode 2 internal clock TRM == write preload Input External Timer Event Counter ModeMode 3 internal clock TRM = TIO Cpuclk + 10.Event Counter Mode, TRM = = write compare Clock Input Signal Measurement ModesMeasurement Input Width Mode Input width Measurement Mode 4 internal clock TRM = Mode 4 internal clock TRM = 1 first event First event = write preload = write compare Measurement Input Period ModeMode 5 internal clock TRM = Input period Measurement Internal Reads TCR period Counting, doesMay occur TOF=1 Interrupt Service reads TCR delay = M N clock periods Measurement Capture ModeMode 6 internal clock TRM = Internal Pulse width modulation Pulse Width Modulation PWM, ModePWM Mode 7 internal clock TRM = 16.Pulse Width Modulation Toggle Mode, TRM = 17.Pulse Width Modulation Toggle Mode, TRM = Pulse Watchdog Watchdog Pulse ModeWatchdog Modes Output Internal = write preload First event Mode 9 internal clock TRM =Software does not reset watchdog timer watchdog times out Watchdog Output Watchdog Toggle ModeMode 10 internal clock TRM = Toggle DMA Trigger Triple Timer Module Programming ModelSpecial Cases Prescaler Counter 23 22 21 20 19 18 17 Timer Prescaler LoadRegister Tplr Tplr = $FFFF83 PS1 PS0 Timer Prescaler Load Register TplrPrescaler Source Prescaler Preload Value TCF TOF PCE Timer Prescaler Count Register TpcrTimer Control/Status Register Tcsr TRM INV Prescaler Clock Enable Timer Compare FlagTimer Overflow Flag Data Output Inverter Timer Reload ModeDirection Timer Control Number Function Timer Enable Timer Compare Interrupt EnableTimer Overflow Interrupt Enable TIO Programmed as Input TIO Programmed as Output Mode INV = Positive polarity Timer Load Register TLRPulse generated by Timer has Timer has negative Timer Compare Register Tcpr Timer Count Register TCR Appendix a DSP56301 User’s Manual HBS Can be stopped Hdben Aarv Mscte EQU LOOP0 Lbld Lble LOOP8 LOOP11 Rep Mac x0,x1,a x,lr0+ ORG PL,PL Patterns Write to Destination DSP56301 User’s Manual Chapter B Programming Reference Table B-1.Guide to Programming Sheets Bit Address Register Name Internal I/O Memory MapTable B-2. Internal I/O Memory Map X Data Memory Table B-2.Internal I/O Memory Map X Data Memory Peripheral Bit Address Register Name $FFCB $FFFFCB $FFCD $FFFFCD$FFCC $FFFFCC $FFCA $FFFFCA $FFBA $FFFFBA Essi $FFBC $FFFFBC$FFBB $FFFFBB $FFB9 $FFFFB9 $FFAA $FFFFAA Essi $FFAC $FFFFAC$FFAB $FFFFAB $FFA9 $FFFFA9 $FFFF90 $FFFF92$FFFF91 $FF8F $FFFF8F Interrupt Sources and Priorities Table B-3. Interrupt Sources VBA$6C Table B-3.Interrupt SourcesVBA$6A VBA$6E Nonmaskable Host Command Interrupt Table B-4.Interrupt Source Priorities Within an IPL ESSI0 receive last slot interrupt Programming Sheets Figure B-1.Status Register SR Memory Switch Mode External Bus DisableStop Delay Burst Mode Enable Irqb Mode Irqd ModeIrqc Mode Irqa Mode Interrupt Priority Register Iprp $FFFFFE Read/Write Triple Timer IPLHost IPL PLL Control Register Pctl $FFFFFD Read/Write Crystal Range Bit Xtlr Bus Request Hold, Bit Default Area Wait Control, BitsBus Control Register BCR $FFFFFB Read/Write Bus Lock Hold, Bit Dram Control Register DCR $FFFFFA Read/Write Bus X Data Memory Enable, Bit Bus Packing Enable, BitBus Y Data Memory Enable, Bit Bus Program Memory Enable, Bit Reset = $000000 $FFFFE4, X$FFFFE8, X$FFFFEC Read/Write DMA Control Registers DCR5-DCR0 DSP Control Register Dctr Read/Write Address X FFFFC5 Application = Enables master receive interrupts DSP PCI Control Register Dpcr Address XFFFFC6 Read/Write Figure B-12.DSP PCI Master Control Register Dpmc PCI Bus Command, Bits Figure B-13.DSP PCI Address Register Dpar HI32 Control Register Hctr Read/Write HI32 Command Vector Register Hcvr Read/Write Host Non-Maskable Interrupt, Bit Signalled Target Abort, Bit Detected Parity Error, BitSignaled System Error, Bit System Error Enable, Bit Header Type, Bits Latency Timer High, BitsRead/Write Cache Line Size, Bits PCI Mode Base Address High, Bits Pre-fetch, Bit HI32 Memory Space Base Address Configuration Register CbmaReset = $00000000 Memory Space Indicator, Bit Subsystem ID Register, Bits 31-16 Specifies the subsystem ID Essi Control Register a CRAx ESSI0-X$FFFFB5 Read/Write ESSI1-X$FFFFA5 Read/Write ESSI1-X$FFFFA6 Read/Write Essi Control Register B CRBxESSI0-X$FFFFB6 Read/Write Essi Transmit Slot Mask B TSMB0-1 ESSI0-X$FFFFB3 Read/Write Essi Transmit Slot Mask a TSMA0-1 ESSI0-X$FFFFB4 Read/WriteESSI1-X$FFFFA4 Read/Write ESSI1-X$FFFFA3 Read/Write SCI Control Register SCR $FFFF9C Read/Write Clock Out Divider SCI Clock Control Register Sccr Address X$FFFF9B Read/WriteReceiver Clock Mode/Source Figure B-25.Timer Prescaler Load Register Tplr Timer Prescaler Load Register Tplr $FFFF83 Read/Write Timer Control/Status Register TCSR0$FFFF8F Read/Write TCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/Write Timer Load Register TLR0-2 TLR0-X$FFFF8E Write Only TLR1-X$FFFF8A Write Only TLR2-X$FFFF86 Write Only Host Data Register HDR $FFFFC9 Write Port B HI08Host Data Direction Register Hddr X$FFFFC8 Write Port C Direction Register Prrc $FFFFBE Read/Write Port C ESSI0Port C Control Register Pcrc $FFFFBF Read/Write Port C Gpio Data Register Pdrc $FFFFBD Read/Write Port D Direction Register Prrd $FFFFAE Read/Write Port D ESSI1Port D Control Register Pcrd $FFFFAF Read/Write Port D Gpio Data Register Pdrd $FFFFAD Read/Write Port E Direction Register Prre $FFFF9E Read/Write Port E SCIPort E Control Register Pcre $FFFF9F Read/Write Port E Gpio Data Register Pdre $FFFF9D Read/Write Programming Sheets DSP56301 User’s Manual Index Index-2 DSP56301 User’s Manual Index-3 Index-4 DSP56301 User’s Manual Index-5 Index-6 DSP56301 User’s Manual Index-7 Index-8 DSP56301 User’s Manual Index-9 Index-10 DSP56301 User’s Manual Index-11 Index-12 DSP56301 User’s Manual Index-13 Index-14 DSP56301 User’s Manual Index-15 Index-16 DSP56301 User’s Manual