DSP-Side Registers

DCTR

DSP Control Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DPCR

DSP PCI Control Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DPMC

DSP PCI Master Control Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DPAR

DSP PCI Address Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSR

DSP Status Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSP DMA Data Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSP Global Data Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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DPSR

 

DPCR

 

 

DPMC

 

DPAR

 

 

DCTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration Space

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CDID

 

 

 

CVID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CSTR

 

 

CCMR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CCCR

 

 

 

CRID

 

 

 

 

 

HCVR

 

HSTR

 

 

 

CHTY

CLAT

CCLS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CBMA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CSID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CILP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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HOST Bus

Overview

DPSR

DSP PCI Status Register

 

 

DRXR

DSP Receive Data Register

 

 

DTXM

DSP Master Transmit Data Register

 

 

DTXS

DSP Slave Transmit Data Register

 

 

DIRH

DSP Host Port GPIO Direction Register

 

 

DATH

DSP Host Port GPIO Data Register

 

 

 

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DSR

 

DRXR

 

DTXM

 

DTXS

 

 

DIRH

 

DATH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6 words deep

 

 

 

8 words deep

 

 

 

 

 

6 words deep

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HCTR

 

HTXR

 

HRXM

 

HRXS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24

 

 

 

 

 

 

 

24

 

 

 

 

 

24

 

 

 

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

data transfer format converter

 

 

 

 

 

 

 

 

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32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Host-Side Registers

CDID/CVID

Device ID/Vendor ID Configuration Register

 

 

 

CSTR/CCMR

Status/Command Configuration Register

HCTR

Host Interface Control Register

 

 

 

 

CCCR/CRID

Class Code/Revision ID Configuration Register

 

 

 

HSTR

Host Interface Status Register

 

 

 

 

CHTY/CLAT/

Header Type/Latency Timer Configuration Register

 

 

 

HCVR

Host Command Vector Register

 

 

CCLS

Cache Line Size Configuration Register

 

 

 

HRXM

Host Master Receive Data Register

 

 

 

 

CBMA

Memory Space Base Address Configuration Register

 

 

 

HRXS

Host Slave Receive Data Register

 

 

 

 

CSID

Subsystem Vendor ID Configuration Register

 

 

 

HTXR

Host Transmit Data Register

 

 

 

 

CILP

Interrupt Line-Interrupt Pin Configuration Register

 

 

 

 

 

 

 

 

Note: As the PCI master, the HI32 uses the HRXM to output data. The host bus cannot access this register.

Figure 6-1.HI32 Block Diagram

In Self-Configuration mode (DCTR[HM] = $5), the DSP56300 core can indirectly write all registers in the PCI Configuration Space but the CDID/DVID register. The HI32 cannot read any of the registers in its configuration space. Host processors can use standard host processor instructions and addressing modes to communicate with the HI32 registers. The host processor can be any of a number of industry-standard microcomputers or microprocessors,

Host Interface (HI32)

6-5

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Motorola DSP56301 user manual DSP-Side Registers, DSP DMA Data Bus DSP Global Data Bus, PCI Configuration Space
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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