Index

adder modulo 1-7offset 1-7

reverse-carry 1-7

Address Arithmetic Logic Unit (Address ALU) 1-7Address Attribute 0–3 ( AA[0–3]) 2-6

Address Attribute Priority Disable (APD) bit 4-13Address Attribute Registers (AAR) 4-22,4-27

Bus Access Type (BAT) 4-29

Bus Address Attribute Polarity (BAAP) 4-28Bus Address to Compare (BAC) 4-27

Bus Number of Address Bits to Compare (BNC) 4-27Bus Packing Enable (BPAC) 4-28

Bus Program Memory Enable (BPEN) 4-28

Bus X Data Memory Enable (BXEN) 4-28

Bus Y Data Memory Enable (BYEN) 4-28programming sheet B-20

address bus external 2-6signals 2-1,2-6

Address Generation Unit (AGU) 1-7Address Mode Wakeup 8-3Address Trace Enable (ATE) bit 4-13Address Trace mode 1-5addressing modes 1-4,1-8Alignment Control (ALC) bit 7-16Arithmetic Saturation Mode (SM) bit 4-7Asynchronous Bus Arbitration Enable (ABE) bit 4-13asynchronous data transfer 8-2

Asynchronous mode 7-10,8-2,8-15,8-17,8-18Asynchronous Multidrop mode 8-17

barrel shifter 1-4,1-6baud rate generator 1-6bit-oriented instructions 5-2bootstrap 3-1,3-3

code 8-8program 4-5

program options, invoking 4-6ROM 1-5

Boundary Scan Register (BSR) 4-35Burst Mode Enable (BE) bit 4-14bursts 6-4

bus

address signals 2-1data signals 2-1,2-6external address 2-6external data 2-6internal 1-10

Bus Access Type (BAT) bits 4-29

Bus Address Attribute Polarity (BAAP) bit 4-28Bus Address to Compare (BAC) bits 4-27

Bus Area 0 Wait State Control (BA0W) bits 4-24Bus Area 1 Wait State Control (BA1W) bits 4-23Bus Area 2 Wait State Control (BA2W) bits 4-23Bus Area 3 Wait State Control (BA3W) bits 4-23Bus Busy (BB) 2-8

Bus Clock (BCLK) 2-8 Bus Clock Not (BCLK) 2-8

Bus Column In-Page Wait State (BCW) bit 4-26Bus Control Register (BCR) 4-22

Bit Definitions 4-22

Bus Area 0 Wait State Control (BA0W) 4-24Bus Area 1 Wait State Control (BA1W) 4-23Bus Area 2 Wait State Control (BA2W) 4-23Bus Area 3 Wait State Control (BA3W) 4-23

Bus Default Area Wait State Control (BDFW) 4-23Bus Lock Hold (BLH) bit 4-22

Bus Request Hold (BRH) 4-22Bus Request Hold (BRH) bit 4-22Bus State (BBS) bit 4-22programming sheet B-18

bus control signals 2-1

Bus Default Area Wait State Control (BDFW) bits 4-23Bus DRAM Page Size (BPS) bit 4-26

Bus Grant (BG) 2-8

Bus Interface Unit (BIU)

Address Attribute Registers (AAR) 4-22

Bus Control Register (BCR) 4-22

DRAM Control Register (DCR) 4-22

Bus Lock (BL) 2-8

Bus Mastership Enable (BME) bit 4-25

Bus Number of Address Bits to Compare (BNC) bits 4-27Bus Packing Enable (BPAC) bit 4-28

Bus Page Logic Enable (BPLE) bit 4-26

Bus Program Memory Enable (BPEN) bit 4-28Bus Refresh Enable (BREN) bit 4-25

Bus Refresh Prescaler (BRP) bit 4-25Bus Refresh Rate (BRF) bit 4-25Bus Release Timing (BRT) bit 4-14Bus Request (BR) 2-7

Bus Request Hold (BRH) bit 4-22

DSP56301 User’s Manual

Index-1

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Index

Models: DSP56301

Index

DSP56301 User’s Manual

Index-1

DSP56301 specifications