HI32 DSP-Side Programming Model

6.7.1DSP Control Register (DCTR)

The DCTR is a 24-bit read/write control register by which the core controls the HI32 interrupts, flags, and host port pin functionality. The host processor cannot access the DCTR. To access individual DCTR bits, use the bit manipulation instructions.

.

 

23

22

 

 

 

 

21

 

20

 

19

18

 

17

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HM2

 

 

 

HM1

 

HM0

 

HIRD

HIRH

 

HRSP

 

HDRP

 

 

 

All modes

 

 

All modes

All modes

UB

UB

UB

UB

 

 

15

14

 

 

 

 

13

 

12

 

11

10

 

9

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HTAP

HRWP

 

 

HDSM

 

 

 

 

 

 

 

 

 

 

 

 

UB

UB

 

 

 

UB

 

 

 

 

 

 

 

 

 

 

 

7

6

 

 

 

 

5

 

4

 

3

2

 

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HINT

 

 

 

HF5

 

HF4

 

HF3

SRIE

 

STIE

 

HCIE

 

 

 

UB/PCI

 

 

UB/PCI

UB/PCI

UB/PCI

UB/PCI

UB/PCI

UB/PCI

 

 

 

Reserved. Write to 0 for future compatibility

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UB = Universal Bus mode

PCI = PCI mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6-5.DSP Control Register (DCTR)

 

 

 

 

 

 

Table 6-10.DSP Control Register (DCTR) Bit Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit Number

Bit Name

 

Reset

 

Mode

 

 

 

Description

 

 

 

 

 

 

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23

 

 

0

 

 

 

 

Reserved. Write to 0 for future compatibility.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22–20

HM[2–0]

 

0

 

 

All

HI32 Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

modes

Control the operation modes and pin functionality of the HI32. Values

 

 

 

 

 

 

 

 

 

 

 

are as follows:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

000

 

Terminate and Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

001

 

PCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

010

 

Universal Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

011

 

Enhanced Universal Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

100

 

GPIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

101

 

Self Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

110

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

111

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Host Interface (HI32)

6-23

Page 141
Image 141
Motorola DSP56301 user manual DSP Control Register Dctr, Bit Number Bit Name, Mode Description Value

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.