DSP PCI Address Register Dpar, BE2 BE1 | Motorola DSP56301 instruction

HI32 DSP-Side Programming Model

6.7.4DSP PCI Address Register (DPAR)

23		22		21		20		19	18	17	16

	BE3		BE2		BE1		BE0	C3	C2	C1	C0

15		14		13		12		11	10	9	8

AR15		AR14		AR13		AR12		AR11	AR10	AR9	AR8

7		6		5		4		3	2	1	0

AR7		AR6		AR5		AR4		AR3	AR2	AR1	AR0

Figure 6-8.DSP PCI Address Register (DPAR)

A 24-bit read/write register by which the DSP56300 core generates the two least significant bytes of the 32-bit PCI transaction address, the PCI bus command and the PCI bus byte enables. The host processor cannot access DPAR. The two most significant bytes of the PCI transaction address are located in the DSP PCI Master Control register (DPMC, see Section 6.7.3, DSP PCI Master Control Register (DPMC), on page 6-30).

When the DSP56300 core writes to DPAR in PCI mode (DCTR[HM] = $1), DPSR[MARQ] is cleared.1 When the HI32 can complete the first data phase,2ownership of the PCI bus is requested. When the request is granted, the address (from the DPMC and the DPAR) is driven to the HAD[31– 0] pins and the bus command is driven to the HC[3–0]/HBE[3–0]pins during the PCI address phase. The DPAR can be written only if MARQ is set.

Table 6-13.DSP PCI Address Register (DPAR) Bit Definitions

Bit Number	Bit Name		Reset Value	Description


23–20			0	PCI Byte Enables
23–20		BE[3–0]	0	PCI Byte Enables
				Determine which byte lanes carry meaningful data in PCI mode
				(DCTR[HM] = $1) when the HI32 is a PCI master. BE3 applies to byte 3,
				and BE0 to byte 0. Byte enables are driven to HC[3–0]/HBE[3–0] pins
				during the PCI data phases. As master, the HI32 drives all the HRXM
				data to the HAD[31–0] pins during write transactions and writes the
				HAD[31–0] pins to the HTXR (in accordance with the FC[1–0] bits) in
				read transactions, regardless of the BE[3–0] value.

				Note: The PCI host must not change the values of the	BE[3–0]	bits
				during PCI read transactions from the HI32 as a PCI target.

1.DPSR[MARQ] is the PCI Master Address Request bit in the DSP PCI Status Register. This bit indicates that the HI32 is currently not the initiator of a PCI transaction and the DPAR can be written with the address of the next transaction.

2.That is, in a write transaction, the DSP-to-host data path is not empty; in a read transaction, the host-to-DSP data path is not full.

Host Interface (HI32)

6-33

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual DSP PCI Address Register Dpar Bit Definitions, BE2 BE1

Models: DSP56301