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Motorola DSP56301 user manual Enhanced Serial Synchronous Interface, PD0, PD1, PD2

Models: DSP56301

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Enhanced Synchronous Serial Interface 1

2.9Enhanced Synchronous Serial Interface 1

Table 2-14.Enhanced Serial Synchronous Interface 1

	Signal Name	Type	State During	Signal Description
	Signal Name	Type	Reset	Signal Description
			Reset


	SC10	Input or Output	Input	Serial Control 0—For asynchronous mode, this signal is
				used for the receive clock I/O (Schmitt-trigger input). For
				synchronous mode, this signal is used either for transmitter 1
				output or for serial I/O flag 0.
				Port D 0—The default configuration following reset is GPIO
				input PD0. When configured as PD0, signal direction is
		Input or Output		controlled through the port directions register (PRR1). The
	PD0			signal can be configured as an ESSI signal SC10 through the
				port control register (PCR1).
				This signal has a weak keeper to maintain the last state even
				if all drivers are tri-stated.

	SC11	Input/	Input	Serial Control 1—For asynchronous mode, this signal is the
		Output		receiver frame sync I/O. For synchronous mode, this signal is
				used either for Transmitter 2 output or for Serial I/O Flag 1.
				Port D 1—The default configuration following reset is GPIO
				input PD1. When configured as PD1, signal direction is
				controlled through PRR1. The signal can be configured as an
				ESSI signal SC11 through PCR1.
	PD1	Input or Output
				This signal has a weak keeper to maintain the last state even
				if all drivers are tri-stated.

	SC12	Input/	Input	Serial Control Signal 2—For frame sync I/O. SC12 is the
		Output		frame sync for both the transmitter and receiver in
				synchronous mode, and for the transmitter only in
				asynchronous mode. When configured as an output, this
				signal is the internally generated frame sync signal. When
				configured as an input, this signal receives an external frame
				sync signal for the transmitter (and the receiver in
				synchronous operation).
				Port D 2—The default configuration following reset is GPIO
	PD2	Input or Output		input PD2. When configured as PD2, signal direction is
				controlled through PRR1. The signal can be configured as an
				ESSI signal SC12 through PCR1.
				This signal has a weak keeper to maintain the last state even
				if all drivers are tri-stated.

Signals/Connections

2-25

Image 55

Motorola DSP56301 user manual Enhanced Serial Synchronous Interface, PD0, PD1, PD2

Contents

Revision 3, March DSP56301 User’s ManualASIA/PACIFIC How to reach usUSA/EUROPE JapanPage Page Contents Chapter Core Configuration Chapter Memory ConfigurationChapter Host Interface HI32 Chapter Programming the PeripheralsChapter Enhanced Synchronous Serial Interface Essi Chapter Serial Communication Interface SCI Chapter a Bootstrap Program Chapter B Programming Reference Chapter Triple Timer ModuleIndex DSP56301 User’s Manual FiguresXii Pulse Width Modulation Toggle Mode, TRM = DSP Control Register Dctr DSP PCI Control Register Dpcr Tables TablesEssi Clock Sources Overview Manual OrganizationGround2 High True/Low True Signal ConventionsSignal/Symbol Logic State Signal State Voltage Manual ConventionsPIN is a generic term for any pin on the chip GroundDSP56300 Core Features CE = MS = Program RAM Instruction Data RAM Switch Size Cache SizeSize Cache Data ALU DSP56300 Core Functional BlocksData ALU Registers Address Generation Unit AGUMultiplier-Accumulator MAC Program Control Unit PCU Jtag TAP and OnCE Module PLL and Clock OscillatorInternal Buses DSP56301 Switch Memory ConfigurationOn-Chip Memory Memory Expansion Area DMAExpansion Area Enhance Synchronous Serial Interface Essi General-Purpose Input/Output Gpio signalsPeripherals Host Interface HI32Serial Communications Interface SCI Triple Timer ModuleDSP56300FM/AD Related Documents and Web SitesDSP56301 Documentation Name Description Order NumberESSI1 DSP56301 Functional Signal GroupingsTimers JTAG/OnCE Port Enhanced Synchronous Serial Interfaces ESSI0DSP56301 See -2for a listing of the Host Interface/Port B SignalsPort a Host Interface/Port B Detail Signal Diagram Ground PowerPower Inputs Ground SignalsPLL Clock SignalsPhase-Lock Loop Signals ClockExternal Bus Control External Memory Expansion Port Port aExternal Address Bus External Data BusOutput Tri-stated Is asserted for half a clock Signals are tri-statedArbitration is reset to the bus slave state Output Tri-stated Is an active-low output that isBclk CASNonmaskable Interrupt-After Interrupt and Mode ControlInterrupt and Mode Control Signal State Type During Signal Description Name10.Host Interface Host Interface HI32Command 0-3/Byte Enable 0-3 -When the HI32 is programmed Hperr HBSHpar HdakHWR HserrHirq HstopSignal PCI Mode Enhanced Universal Bus Mode Gpio Mode Name 11.Summary of HI32 Signals and ModesHAD12 HD4 HIO12 HP8 HAD8 HD0 HIO8 HP9 HAD9 HD1 HIO9HAD10 HD2 HIO10 HAD11 HD3 HIO11PCI 12.Host Port Pins HI32Gpio Host Initiator Ready Host Data Bus Direction Bus Command/Byte Enable Host Address BusHost Target Ready Host Data Bus Enable ReservedHost Lock Bus Strobe Parity Error DMA RequestBus Grant Host Address Enable Host Device Select Host Select AcknowledgeHstr Host System Error Host Interrupt RequestBus Request Host Transfer Acknowledge Hreq is deasserted in the same PCIInitialization Device Select Host Read/Data Strobe Hstop HWR/HRWHost Stop Host Write/Read-Write HRD/HDSAddress/Data Multiplexed Bus Data Bus Host Bus ClockActive low, open drain output pin Hardware ResetEnhanced Synchronous Serial Interface Host Interrupt aPC2 13.Enhanced Synchronous Serial InterfacePC0 PC1PC4 SCK0PC3 SRD0PD2 14.Enhanced Serial Synchronous InterfacePD0 PD1PD4 SCK1PD3 SRD1Serial Communications Interface SCI Timers15.Serial Communication Interface Timer 2 Schmitt-Trigger Input/Output- When timer 16.Triple Timer SignalsTimer 0 Schmitt-Trigger Input/Output- When Timer Timer 1 Schmitt-Trigger Input/Output- When TimerJtag and OnCE Interface Signal Name Type State During Signal Description Reset17.JTAG/OnCE Interface Jtag and OnCE Interface DSP56301 User’s Manual Program Memory Space Memory ConfigurationInternal Program Memory Memory Switch Modes-Program MemoryInstruction Cache Data Memory Space Program Bootstrap ROMMemory Switch Modes-X Data Memory Memory ConfigurationInternal I/O Space-X Data Memory Memory Switch Modes-Y Data MemoryInternal Y Data Memory External I/O Space-Y Data Memory Dynamic Memory Configuration SwitchingDSP56301 RAM Address Ranges by Configuration Sixteen-Bit Compatibility Mode ConfigurationInternal Memory Configuration Summary DSP56301 RAM ConfigurationsMemory Maps DefaultRAM None 64K $000-$FFF $000-$7FF 16-Bit Space With Default RAM 0, 0$000-$800 $000-$BFF 16MNone 64K $000-$7FF $000-$BFF 16-Bit Space With Switched Program RAM 0, 1$000-$BFF $000-$7FF Not addressable Instruction Cache Enabled 1, 016-Bit Space With Instruction Cache Enabled 1, 0 $000-$3FF $000-$BFF Not addressable Addressable$0400 $0000 Core Configuration Core ConfigurationMode Reset Description VectorOperating Modes DSP56301 Operating ModesMode Description Operating Mode DefinitionsLow. The DSP56301 is written with 24-bit-wide words Address attributes selected defaultDSP Clkout rate must be 5/3 of the PCI clock Bootstrap Program Status Register SR Central Processor Unit CPU RegistersDMA OMR Do Loop Flag Cache EnableSixteen-Bit Arithmetic Mode Do Forever FlagSixteen-Bit Compatibility Mode Priority Exceptions Exceptions Masked Permitted Scaling ModeScaling Rounding Bit SEquation Mode Interrupt MaskUnnormalized Bit Number Bit Name Reset Value Description LimitScaling Mode Integer Portion ExtensionStack Extension Wrap Flag Operating Mode Register OMROperating Mode Register OMR Bit Definitions Stack Extension EnableStack Extension Overflow Flag Address Trace EnableAddress Attribute Priority Disable Asynchronous Bus Arbitration EnableSynchronize Select Cache Burst Mode EnableMemory Switch Mode Bus Release TimingChip Operating Mode Configuring InterruptsBit Number Bit Name Reset Value Description Stop Delay Mode External Bus DisableInterrupt Priority Registers Iprc and Iprp Interrupt Priority Level Bits Interrupt Table Memory MapInterrupt Sources VBA$2A VBA$1AVBA$1C VBA$1EInterrupt Source Priorities Within an IPL Processing Interrupt Source Priorities Within an IPLPriority Interrupt Source TIMER1 overflow interrupt Host command interruptTIMER0 overflow interrupt TIMER0 compare interruptPLL Control Register Pctl Bit Definitions PLL Control Register PctlBus Control Register Bus Interface Unit BIU RegistersBus Area 1 Wait State Control Bus Default Area Wait State ControlBus Area 3 Wait State Control Bus Area 2 Wait State ControlBstr Bren BME Bple BPS1 Dram Control Register DCRBRP BRF7 BRF6 BRF3 BRF2 BRF110.DRAM Control Register DCR Bit Definitions Bus Column In-Page Wait State Bus Page Logic EnableBus Dram Page Size Bus Row Out-of-page Wait StatesBus Address to Compare Address Attribute Registers AAR0-3Bus Number of Address Bits to Compare Bus Program Memory Enable Bus Packing EnableBus Y Data Memory Enable Bus X Data Memory EnableDAM5 DAM4 DAM3 DAM2 DAM1 DAM0 DMA Control Registers 5-0 DCR5-0DIE DTM2 DTM1 DTM0 Dcon12.DMA Control Register DCR Bit Definitions DMA Interrupt EnableDMA Transfer Mode DTM2-0 Trigger Cleared Transfer Mode AfterDPR1-0 Channel Priority Number ValueDMA Channel Priority DMA address generation logic, buses, and so forthOMR CDP1-0 CP1-0 Core Priority DMA Continuous Mode EnableDcon DMA Request Source Three-Dimensional ModeDRS4-0 Requesting Device DDS1 DDS0 Device Identification Register IDRDSS1 DSS0 Number Identity See Note Jtag Identification ID RegisterJtag Boundary Scan Register BSR Version Information Design CenterJtag Boundary Scan Register BSR DSP56301 User’s Manual Programming the Peripherals Peripheral Initialization StepsData Memory Mapping the Control RegistersData Transfer Methods PollingInterrupts 3 DMA General-Purpose Input/Output GpioAdvantages and Disadvantages Host Interface/Port B Detail Signal Diagram Port B Signals and RegistersPort D Signals and Registers Port C Signals and RegistersPort E Signals and Registers Timer Gpio Triple Timer Signals and RegistersGeneral-Purpose Input/Output Gpio DSP56301 User’s Manual Host Interface HI32 FeaturesHI32 Features, Core-Side and Host-Side HI32 Features in PCI Mode and Universal Bus Mode Overview Data transfer format converter PCI Configuration SpaceDSP-Side Registers DSP DMA Data Bus DSP Global Data BusHost-to-DSP Data Path Data Transfer PathsDSP-To-Host Data Path Two least significant bytes of two Hrxm HI32 PCI Master Data Transfer FormatsDpmc FC1 FC0Hctr Transmit Data Transfer FormatHTF1 HTF0 Three least significant Hrxs bytes Receive Transfer Data FormatsDSP to Host Data Transfer Format HRFReceive Transfer Data Formats HRST/HRST Reset StatesType Entered when Description DSP-Side Operating ModesPCI Terminate and Reset Dctrhm = $0PCI Mode Dctrhm = $1 HI32 ModeExample 6-1. PCI /DMA Throughput 32-Bit Multfactor Self-Configuration Mode Dctrhm = $5 Gpio Mode Dctrhm = $4Example 6-3. Self-Configuration Procedure for PCI Mode PCI Bus Universal Bus Mode Host Port PinsHost Port Pin Functionality DSP56301 ISA Slave MasterHI32 DSP-Side Programming Model Memory Register Address ModeHI32 Programming Model, DSP Side DSP Control Register Dctr Mode Description ValueBit Number Bit Name 10.DSP Control Register Dctr Bit Definitions Host Read/Write Polarity Host Data Strobe ModeHtap Host Transfer Acknowledge PolarityDSP PCI Control Register Dpcr Slave Receive Interrupt EnableSlave Transmit Interrupt Enable Host Command Interrupt EnableIAE Insert Address EnableReceive Buffer Lock Enable 11.DSP PCI Control Register Dpcr Bit DefinitionsHserr Master Wait State DisableMaster Access Counter Enable ForceParity Error Interrupt Enable Transfer Complete Interrupt EnableTransaction Termination Interrupt Enable Transaction Abort Interrupt EnableBL4 DSP PCI Master Control Register DpmcBL1 BL0 A PCI Host-to-DSP transaction 12.DSP PCI Master Control Register Dmpc Bit DefinitionsData Transfer Format Control A PCI DSP-to-Host transactionDSP PCI Transaction Address High PCI Data Burst LengthAR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 DSP PCI Address Register Dpar13.DSP PCI Address Register Dpar Bit Definitions BE2 BE1AR1 AR0 PCI Bus CommandC3-0 Command Type DSP PCI Transaction Address Low2322212019181716 Bit Bit Name Reset Mode Description Number ValueDSP Status Register DSR 14.DSP Status Register DSR Bit DefinitionsSlave Receive Data Request Srrq UBMSlave Transmit Data Request Mode Description Number ValueHost Command Pending 14. DSP Status Register DSR Bit DefinitionsAper Marq Mrrq Mtrq MWS DSP PCI Status Register Dpsr15.DSP PCI Status Register Dpsr Bit Definitions Rdcq MDT Hdtc Trty Tdis TAB MABPCI Target Retry Master Data TransferredPCI Host Data Transfer Complete PCI Time Out TerminationPCI Target Abort PCI Data Parity ErrorPCI Address Parity Error PCI Target DisconnectPCI Master Receive Data Request DSP Receive Data Fifo Drxr15. DSP PCI Status Register Dpsr Bit Definitions PCI Master Wait StatesDSP Slave Transmit Data Register Dtxs DSP Master Transmit Data Register DtxmDSP Host Port Gpio Data Register Dath DSP Host Port Gpio Direction Register Dirh16.DATH and Dirh Functionality 17.HI32 Programming Model, Host-Side Registers Host-Side Programming ModelMemory Register Host-Side Programming Model Ignored 18.PCI Bus CommandsExecuted as Command Type HC3/HBE3-HC0/HBE021. Host-Side Registers Universal Bus Mode Address Space 20. Host-Side Registers PCI Configuration Address Space19. Host-Side Registers PCI Memory Address Space 13.Host Interface Control Register Hctr 1 HI32 Control Register HctrTwsd PCI Bit Bit Name Reset Mode Description NumberTarget Wait State Disable 22.Host Interface Control Register Hctr Bit DefinitionsHost Receive Data Transfer Format Host Transmit Data Transfer Format SFT UBM Inserted AddressSlave Fetch Type Data path is lost when the reset state is Universal Bus mode Fetch SFT =Cleared when the DSP56300 core writes to Reset, and Strq and Hstrhrrq are clearedDmae Haen Dmae UBMHirq Hirq Pin Hdrq pin Receive Req uest EnableRreq UBM Dmae Treq RreqUBM UBM UBM UBM UBM UBM PCI PCI PCI PCI PCI PCI Host Interface Status Register HstrHreq Hint HF5 HF4 HF3 TrdyTreq Rreq Hreq 23.Host Interface Status Register Hstr Bit DefinitionsHost Request Host interrupt aHost Transmit Data Request Host Receive Data RequestTransmitter Ready 15.Host Command Vector Register Hcvr Host Command Vector Register HcvrHnmi UBM 24.Host Command Vector Register Hcvr Bit DefinitionsHost Command Vector Bit Bit Name Reset Value Mode Description NumberHost Slave Receive Data Register Hrxs Host CommandWhen the DSP56300 core acknowledges the host command Host Master Receive Data Register HrxmHost Transmit Data Register Htxr Universal Bus mode Dctrhm = $2 or $3 PCI Mode Dctrhm = $1DPR Fbbc Device ID/Vendor ID Configuration Register CDID/CVIDStatus/Command Configuration Register CSTR/CCMR DPE SSE RMA RTA STAReceived Master Abort Detected Parity ErrorSignaled System Error Signalled Target AbortBus Master Enable System Error EnableWait Cycle Control hardwired to zero Parity Error ResponseClass Code/Revision ID Configuration Register CCCR/CRID Read-only bits that identify the layout of bytes $10-$3F Header Type hardwired to $00HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0 HT7-0Cache Line Size Latency Timer HighCcls Memory Base Address High/Low Memory Space Base Address Configuration Register CbmaUniversal Bus Mode Base Address PM8 PM7 PM6 PM5 PM4 MS1 MS0 MSIMemory Space Hardwired to zeros 29. Memory Space Base Address Configuration Register CbmaMemory Base Address Low Hardwired to zeros Pre-Fetch Hardwired to zeroExample 6-5. Code for Setting the Csid Maxlat Interrupt Line-Interrupt Pin Configuration RegisterCILPIL5 IL4 IL1 IL0UBM Hrsp HI32 Programming Model/Quick ReferenceHS PH PS Dctr HcieClrt Dpcr MtieRble Hact DpmcDpar DSR HCPRdcq Dpsr AperDper HdtcSFT TreqDmae ISA/EISAHrxs HcvrHnmi HrxmCbma MSI Ccmr RMACccr ChtySC0 GDB DDB RclkRsma Rsmb Tsma Tclk STD Tsmb TX0 CRAEssi Enhancements Serial Clock SCK Essi Data and Control SignalsSerial Transmit Data Signal STD Serial Receive Data Signal SRDSerial Control Signal SC1 Serial Control Signal SC0Control Bits Essi Signals Mode and Signal DefinitionsSYN TE0 TE1 TE2 SC0 SC1 SC2 SCK STD SRD Initialization Serial Control Signal SC2Essi After Reset OperationExceptions Operation Write data to all enabled transmit registers Operating Modes Normal, Network, and On-Demand Normal/Network/On-Demand Mode SelectionSynchronous/Asynchronous Operating Modes Frame Sync Signal FormatFrame Sync Selection Word Length Frame Sync and Data Word Timing Frame Sync Length for Multiple DevicesFrame Sync Polarity Flags Byte Format LSB/MSB for the TransmitterPM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Essi Programming ModelEssi Control Register a CRA WL2 WL1 WL0 ALCEssi Word Length Selection Essi Control Register a CRA Bit DefinitionsSelect SC1 Word Length ControlPrescale Modulus Select Alignment ControlFrame Rate Divider Control Prescaler RangeTclock CRBTE1 CRBOF0 SSISRIF0Crbsyn = RclockESSI0 X$FFFFB6, ESSI1 X$FFFFA6 Essi Control Register B CRBShfd OF1 OF0Essi Control Register B CRB Bit Definitions TIE Transmit Interrupt EnableReceive Enable Transmit 0 EnableSynchronous/Asynchronous Transmit 1 EnableTransmit 2 Enable Mode SelectFSL1 FSL0 OF0 Serial Control DirectionOF1 Serial Output FlagSerial Clock RX Frame Sync RX Serial Data Serial Clock RX, TX Frame Sync RX, TX Serial DataTX Frame Sync TX Serial Data Essi Bit CRB SYN Bit OperationSSI Control Register B CRB READ/WRITE Bit OperationReceiver Interrupt or DMA Request and Flags Set Frame Sync FSL0 = 0, FSL1 = Data Flags Frame Sync FSL0 = 0, FSL1 = Data Out FlagsReceive Data Register Full Receiver Overrun Error FlagTransmitter Underrun Error Flag Essi Status Register SsisrSerial Input Flag Essi Receive Shift RegisterReceive Frame Sync Flag Transmit Frame Sync FlagEssi Transmit Shift Registers Essi Receive Data Register RXTransmit Registers Receive RegistersMSB Transmit Middle Byte Transmit Low Byte Register 24 BitWL0 Least SignificantTS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 Essi Transmit Data Registers TX2-0Essi Time Slot Register TSR Transmit Slot Mask Registers TSMA, Tsmb15.ESSI Transmit Slot Mask Register B Tsmb RS15 RS14 RS13 RS12 RS11 RS10 Receive Slot Mask Registers RSMA, RsmbRS7 RS6 RS1 RS0Port Control Registers Pcrc and Pcrd Gpio Signals and RegistersPort Direction Registers Prrc and Prrd Essi Port Signal ConfigurationsESSI0/ESSI1 20.Port Data Registers Pdrc X$FFFFBD Pdrd X $FFFFAD Port Data Registers Pdrc and PdrdSerial Communication Interface SCI Serial Communication Interface SCIAsynchronous Mode Synchronous ModeMultidrop Mode Transmitting Data and Address Characters I/O SignalsWired-OR Mode Address Mode WakeupTransmit Data TXD Receive Data RXDSCI Serial Clock Sclk Woms RWU Wake SBK Ssftd SCI After ResetSCI Registers After Reset Reie Sckp Stir Tmie TIE RIE IlieSCI Initialization Preamble, Break, and Data Transmission Priority Exceptions Bootstrap Loading Through the SCI Boot Mode 2 or aSCI Programming Model Bit Asynchronous 1 Start, 8 Data, 1 Even Parity, 1 Stop Bit Synchronous Data Shift Register ModeWDS2 WDS1 WDS0 Bit Asynchronous 1 Start, 8 Data, 1 StopSCI Data Word Formats Ssftd = 0 Reie SCI Control Register SCRStir Tmie TIE RIE Ilie Woms RWU Wake SBK Ssftd WDS2 Idle Line Interrupt Enable Timer Interrupt EnableSCI Transmit Interrupt Enable SCI Receive Interrupt EnableWired-OR Mode Select Receiver EnableWoms SCI Shift Direction Receiver Wakeup EnableWakeup Mode Select Send BreakWord Select Mode Word FormatsWDS1 WDS0 SCI Status Register SCI Status Register SSR Bit Definitions SCI Status Register SSRIdle Rdrf Tdre Trne Tdre Idle Line FlagTransmitter Empty Sclk SCI Clock Control Register SccrTCM RCM SCP COD TCM RCMSckp = 0 + Sckp = Bit CounterDivide by CD11-0X1 Clock X16 Clock Sckp = RX, TX Data Ssftd =SCI Receive Register SRX SCI Data RegistersSCI Receive Data Shift Register SCI Transmit Register STX PE2 PE1 PE0 Port E Control Register PcreSclk TXD RXD PDRE1 PDRE0 Port E Direction Register PrrePort E Data Register Pdre PRRE1 PRRE0Gpio Signals and Registers DSP56301 User’s Manual Triple Timer Module Triple Timer ModuleTpcr Triple Timer Module Block DiagramIndividual Timer Block Diagram GDBTimer Module Block Diagram Timer After ResetTimer Exceptions Timer InitializationTCSR0 Tcie TIO Triple Timer ModesTimer Gpio Mode TC3 TC2 TC1 TC0TLR Mode 0 internal clock, no timer output TRM =TCR Tcpr Mode 1 internal clock TRM = Timer Pulse ModeOutput Pulse width = timer clock Period = write preload = write compare Clock CLK/2 or prescale CLK Timer Toggle ModeMode 2 internal clock TRM = 1 first event Toggle Timer= write preload Mode 2 internal clock TRM == write compare Clock CLK/2 or prescale CLK TIO Cpuclk + Timer Event Counter ModeMode 3 internal clock TRM = Input External= write compare Clock 10.Event Counter Mode, TRM =Input width Measurement Signal Measurement ModesMeasurement Input Width Mode InputMode 4 internal clock TRM = 1 first event Mode 4 internal clock TRM =Input period Measurement Internal Measurement Input Period ModeMode 5 internal clock TRM = First event = write preload = write compareMay occur TOF=1 Counting, doesReads TCR period Internal Measurement Capture ModeMode 6 internal clock TRM = Interrupt Service reads TCR delay = M N clock periodsPWM Pulse Width Modulation PWM, ModePulse width modulation 16.Pulse Width Modulation Toggle Mode, TRM = Mode 7 internal clock TRM =17.Pulse Width Modulation Toggle Mode, TRM = Output Internal Watchdog Pulse ModeWatchdog Modes Pulse WatchdogSoftware does not reset watchdog timer watchdog times out Mode 9 internal clock TRM == write preload First event Toggle Watchdog Toggle ModeMode 10 internal clock TRM = Watchdog OutputPrescaler Counter Triple Timer Module Programming ModelSpecial Cases DMA TriggerTplr = $FFFF83 Timer Prescaler LoadRegister Tplr 23 22 21 20 19 18 17Prescaler Preload Value Timer Prescaler Load Register TplrPrescaler Source PS1 PS0TRM INV Timer Prescaler Count Register TpcrTimer Control/Status Register Tcsr TCF TOF PCEData Output Timer Compare FlagTimer Overflow Flag Prescaler Clock EnableDirection Timer Reload ModeInverter Number Function Timer ControlTIO Programmed as Input TIO Programmed as Output Mode INV = Timer Compare Interrupt EnableTimer Overflow Interrupt Enable Timer EnablePulse generated by Timer has Timer has negative Timer Load Register TLRPositive polarity Timer Count Register TCR Timer Compare Register TcprAppendix a DSP56301 User’s Manual HBS Can be stopped Hdben Aarv Mscte EQU LOOP0 Lbld Lble LOOP8 LOOP11 Rep Mac x0,x1,a x,lr0+ ORG PL,PL Patterns Write to Destination DSP56301 User’s Manual Programming Reference Chapter BTable B-1.Guide to Programming Sheets Table B-2. Internal I/O Memory Map X Data Memory Internal I/O Memory MapBit Address Register Name Peripheral Bit Address Register Name Table B-2.Internal I/O Memory Map X Data Memory$FFCA $FFFFCA $FFCD $FFFFCD$FFCC $FFFFCC $FFCB $FFFFCB$FFB9 $FFFFB9 Essi $FFBC $FFFFBC$FFBB $FFFFBB $FFBA $FFFFBA$FFA9 $FFFFA9 Essi $FFAC $FFFFAC$FFAB $FFFFAB $FFAA $FFFFAA$FF8F $FFFF8F $FFFF92$FFFF91 $FFFF90Table B-3. Interrupt Sources Interrupt Sources and PrioritiesVBA$6E Table B-3.Interrupt SourcesVBA$6A VBA$6CTable B-4.Interrupt Source Priorities Within an IPL Nonmaskable Host Command InterruptESSI0 receive last slot interrupt Figure B-1.Status Register SR Programming SheetsBurst Mode Enable External Bus DisableStop Delay Memory Switch ModeIrqa Mode Irqd ModeIrqc Mode Irqb ModeHost IPL Triple Timer IPLInterrupt Priority Register Iprp $FFFFFE Read/Write Crystal Range Bit Xtlr PLL Control Register Pctl $FFFFFD Read/WriteBus Lock Hold, Bit Default Area Wait Control, BitsBus Control Register BCR $FFFFFB Read/Write Bus Request Hold, BitDram Control Register DCR $FFFFFA Read/Write Bus Program Memory Enable, Bit Bus Packing Enable, BitBus Y Data Memory Enable, Bit Bus X Data Memory Enable, BitDMA Control Registers DCR5-DCR0 Reset = $000000 $FFFFE4, X$FFFFE8, X$FFFFEC Read/WriteApplication DSP Control Register Dctr Read/Write Address X FFFFC5DSP PCI Control Register Dpcr Address XFFFFC6 Read/Write = Enables master receive interruptsFigure B-12.DSP PCI Master Control Register Dpmc Figure B-13.DSP PCI Address Register Dpar PCI Bus Command, BitsHI32 Control Register Hctr Read/Write Host Non-Maskable Interrupt, Bit HI32 Command Vector Register Hcvr Read/WriteSystem Error Enable, Bit Detected Parity Error, BitSignaled System Error, Bit Signalled Target Abort, BitCache Line Size, Bits Latency Timer High, BitsRead/Write Header Type, BitsMemory Space Indicator, Bit HI32 Memory Space Base Address Configuration Register CbmaReset = $00000000 PCI Mode Base Address High, Bits Pre-fetch, BitSubsystem ID Register, Bits 31-16 Specifies the subsystem ID ESSI1-X$FFFFA5 Read/Write Essi Control Register a CRAx ESSI0-X$FFFFB5 Read/WriteESSI0-X$FFFFB6 Read/Write Essi Control Register B CRBxESSI1-X$FFFFA6 Read/Write ESSI1-X$FFFFA3 Read/Write Essi Transmit Slot Mask a TSMA0-1 ESSI0-X$FFFFB4 Read/WriteESSI1-X$FFFFA4 Read/Write Essi Transmit Slot Mask B TSMB0-1 ESSI0-X$FFFFB3 Read/WriteSCI Control Register SCR $FFFF9C Read/Write Receiver Clock Mode/Source SCI Clock Control Register Sccr Address X$FFFF9B Read/WriteClock Out Divider Timer Prescaler Load Register Tplr $FFFF83 Read/Write Figure B-25.Timer Prescaler Load Register TplrTCSR1$FFFF8B Read/Write TCSR2$FFFF87 Read/Write Timer Control/Status Register TCSR0$FFFF8F Read/WriteTLR1-X$FFFF8A Write Only TLR2-X$FFFF86 Write Only Timer Load Register TLR0-2 TLR0-X$FFFF8E Write OnlyHost Data Direction Register Hddr X$FFFFC8 Write Port B HI08Host Data Register HDR $FFFFC9 Write Port C Gpio Data Register Pdrc $FFFFBD Read/Write Port C ESSI0Port C Control Register Pcrc $FFFFBF Read/Write Port C Direction Register Prrc $FFFFBE Read/WritePort D Gpio Data Register Pdrd $FFFFAD Read/Write Port D ESSI1Port D Control Register Pcrd $FFFFAF Read/Write Port D Direction Register Prrd $FFFFAE Read/WritePort E Gpio Data Register Pdre $FFFF9D Read/Write Port E SCIPort E Control Register Pcre $FFFF9F Read/Write Port E Direction Register Prre $FFFF9E Read/WriteProgramming Sheets DSP56301 User’s Manual Index Index-2 DSP56301 User’s Manual Index-3 Index-4 DSP56301 User’s Manual Index-5 Index-6 DSP56301 User’s Manual Index-7 Index-8 DSP56301 User’s Manual Index-9 Index-10 DSP56301 User’s Manual Index-11 Index-12 DSP56301 User’s Manual Index-13 Index-14 DSP56301 User’s Manual Index-15 Index-16 DSP56301 User’s Manual