DSP56301 User’s Manual

; 7-0). The memory is selected by the Address Attribute AA1 and is

;accessed with 31 wait states.


; The EPROM		bootstrap code expects first			to read	3 bytes	specifying	the
; number	of program words, then 3 bytes specifying					the address to
; start	loading		the program words, and then 3 bytes for each program					word
; to be loaded.			The number of words,	the starting		address, and the program
; words	are	read least significant		byte	first	followed	by the mid and

;then by the most significant byte.

; The program words will			be condensed into 24-bit words and stored in
; contiguous	PRAM	memory	locations	starting	at the	specified	starting
; address.	After	the program words		are read,	program	execution	starts

;from the same address where loading started.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;If MD:MC:MB:MA=x010, then it loads the program RAM from the SCI interface.


; The SCI bootstrap code expects					first	to receive	3 bytes specifying	the
; number	of program		words,	then	3 bytes specifying the address to
; start	loading	the program		words, and then 3 bytes for each program				word
; to be loaded.		The number of words, the starting					address, and the program
; words	are received		least significant			byte first	followed by the mid and

;then by the most significant byte.

; The program words will			be condensed	into 24-bit words and stored in
; contiguous	PRAM	memory	locations starting at the specified starting
; address.	After	reading	the program	words, program execution starts

;from the same address where loading started.

; The SCI is	programmed to work in asynchronous				mode	with	8 data bits,	1
; stop bit	and no parity.	The	clock	source	is external		and the clock
; frequency	must be 16x the	baud	rate.	After	each	byte is received,		it

;is echoed back through the SCI transmitter.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;If MD:MC:MB:MA=x011, then it loads the program RAM from the Host Interface

;programmed to operate in the Universal Bus mode supporting DSP-to-DSP

;glueless connection.

;

; The HI32

bootstrap

code expects

first

to read a 24-bit

word specifying

; the number of program

words,

then a 24-bit word

specifying

the

; address to start loading

the program

words, and then

24-bit

word

for

; each

program

word

to be loaded.

;

; The

program

words

will

stored

in contiguous

PRAM

memory

; locations

starting

the

specified

starting

address.

After

; the

program

words are

read,

program

execution

starts

from

the

same

;address where loading started.

;	The Host Interface	bootstrap	load program may be stopped by setting	the
;	Host Flag 0 (HF0)	in HCTR	register. This will start execution of	the

;loaded program from the specified starting address.

; During the access, the HAEN and HA[10 – 3] pins must be driven low; pins

;HA[2 – 0] select the HI32 registers.

;Before booting through the Host Interface it is recommended that the

A-2	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola user manual DSP56301 User’s Manual

Models: DSP56301

PRAM

PRAM

PRAM

DSP56301 specifications