Host-Side Programming Model

hardware can be used with the handshake flags to transfer data without host processor intervention.

νWhen a host bus is less than 24 bits wide, the unused data pins must be forced or pulled

up or down to VCC or to GND, respectively. For example, for a 16-bit bus (such as an ISA bus), HP[48–41] must be forced or pulled up to V CC or pulled down to GND.

In PCI mode:

νIn memory space read/write transactions, the HI32 occupies 16384 Dwords. The host can access the HTXR FIFO and HRXS FIFO at 16377 Dword locations. These FIFOs appear to the external host as 16377 Dwords of read/write memory. Registers are accessed as 32-bit data words.

νThe HAD[1–0]pins should be zero during the address phase of a transaction. The HI32

responds with a target-disconnect transaction termination with the first data phase if HAD[1–0]≠ $0 during the address phase.

νConfiguration space accesses:

—In read/write transactions, the HI32 occupies 64 Dwords. The configuration

registers are accessed as 32-bit Dwords, so the HAD[1–0]pins must be zero during the address phase. The HI32 ignores the transaction if HAD[1–0]≠ $0 during the

address phase of a configuration transaction.

—In HCTR, HSTR, HCVR, and configuration space register accesses, if all four byte lanes are disabled, the HI32 completes the data phase without affecting any flags or data.

νPCI host-to-DSP data transfers:

—In transfers to the HI32 registers (HCTR, HSTR, HCVR, and all configuration space registers), disabled byte lanes (that is, the corresponding byte enable line is deasserted) are not written and the corresponding bytes do not contain significant data.

—Data is written to the HTXR FIFO in accordance with FC[1– 0] or HTF[1–0] bits, regardless of the value of the byte enable pins (HC3/HBE3– HC0/HBE0).

νIn PCI DSP-to-host data transfers via the HRXS or HRXM, all four byte lanes are driven with data, in accordance with FC[1–0] or HRF[1–0] bits, regardless of the value of the byte enable pins (HC3/HBE3-HC0/HBE0).

νIn HI32-to-PCI agent data transfers, all four byte lanes are driven with data, regardless of the value of the byte enables. As a PCI target, the HI32 executes the PCI bus command as shown in Table 6-18.

Host Interface (HI32)

6-45

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Host-Side Programming Model

Models: DSP56301