Motorola DSP56301 user manual Index-15

Timer Overflow Interrupt Enable (TOIE) 9-32Timer Reload Mode (TRM) 9-30

Timer Count Register (TCR) 9-34

Timer Load Registers (TLR) 9-33

Timer Prescaler Count Register (TPCR) 9-28

Prescaler Counter Value (PC) 9-28

Timer Prescaler Load Register (TPLR) 9-27bit definitions 9-27

Prescaler Preload Value (PL) 9-27Prescaler Source (PS) 9-27

Timer Compare Flag (TCF) bit 9-29

Timer Compare Interrupt Enable (TCIE) bit 9-32Timer Compare Register (TCPR) 9-4,9-34Timer Control (TC) bits 9-31

Timer Control/Status Register (TCSR) 9-3,9-28bit definitions 9-28

Data Input (DI) 9-29Data Output (DO) 9-29Direction (DIR) 9-30Inverter (INV) 9-30,9-32Prescaler Clock Enable (PCE) 9-29programming sheet B-38

Timer Compare Flag (TCF) 9-29

Timer Compare Interrupt Enable (TCIE) 9-32Timer Control (TC) 9-31

Timer Enable (TE) 9-32

Timer Overflow Flag (TOF) 9-29

Timer Overflow Interrupt Enable (TOIE) 9-32Timer Reload Mode (TRM) 9-30

Timer Count Register (TCR) 9-34Timer Enable (TE) bit 9-32

Timer Interrupt Enable (TMIE) bit 8-13Timer Interrupt Priority Level (TOL) bits 4-16Timer Interrupt Rate (STIR) bit 8-12

Timer Load Registers (TLR) 9-4,9-33programming sheet B-39

Timer module 1-13architecture 9-1

timer block diagram 9-2Timer Overflow Flag (TOF) bit 9-29

Timer Overflow Interrupt Enable (TOIE) bit 9-32Timer Prescaler Count Register (TPCR) 9-28

bit definitions 9-28

Prescaler Counter Value (PC) 9-28

Timer Prescaler Load Register (TPLR) 9-4,9-27bit definitions 9-27

Prescaler Preload Value (PL) 9-27Prescaler Source (PS) 9-27programming sheet B-37

Timer Reload Mode (TRM) bit 9-30Timers 2-2

Transaction Abort Interrupt Enable (TAIE) bit 6-29Transaction Termination Interrupt Enable (TTIE) bit 6-29Transfer Acknowledge (TA) 2-7

Transfer Complete Interrupt Enable (TCIE) bit 6-29Transmit 0 Enable (TE0) bit 7-20

Transmit 1 Enable (TE1) bit 7-21Transmit 2 Enable (TE2) bit 7-21Transmit Clock Source (TDM) bit 8-19Transmit Data Register Empty (TDE) bit 7-28Transmit Data Register Empty (TDRE) bit 8-18Transmit Data Registers (TX0–TX2) 7-14,7-33Transmit Data signal (TXD) 8-4

Transmit Enable (TE) bits 7-18

Transmit Exception Interrupt Enable (TEIE) bit 7-19Transmit Frame Sync Flag (TFS) 7-29

Transmit Interrupt Enable (TIE) bit 7-20

Transmit Last Slot Interrupt Enable (TLIE) bit 7-19Transmit Request Enable (TREQ) bit 6-56Transmit Shift Registers 7-30

Transmit Slot Mask Registers (TSMA and TSMB) 7-14,7-33

Transmitter Empty (TRNE) bit 8-18Transmitter Enable (TE) bit 8-14Transmitter Ready (TRDY) bit 6-58Transmitter Underrun Error Flag (TUE) 7-28triple timer module 1-13

TX clock 7-11TXD signal 8-4

U

Universal Bus modes 6-44,6-63

Universal Bus mode 6-15,6-6316-bit 6-48,6-57,6-6324-bit 6-56

Universal Bus Mode Address Space 6-47

Universal Bus Mode Base Address (GB[10–3]) bits 6-70Universal Host Interface 1-5

Unnormalized (U) bit 4-11

V

VBA register 1-8

Vector Base Address register (VBA) 1-8

W

Wait Cycle Control (WCC) bit 6-66

Wakeup Mode Select (WAKE) bit 8-15

Wired-OR Mode Select (WOMS) bit 8-14

Word Length Control (WL) bits 7-15

Word Select (WDS) bits 8-16

Write (WR) 2-7

X

X data memory 3-3

Index-15