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Motorola DSP56301 user manual Exceptions, Bootstrap Loading Through the SCI Boot Mode 2 or a

Models: DSP56301

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Exceptions

After the current character transmission, if two or more of these commands are set, the transmitter executes them in the following order: preamble, break, data.

8.4.2Bootstrap Loading Through the SCI (Boot Mode 2 or A)

When the DSP comes out of reset, it checks the MODD, MODC, MODB, and MODA pins and sets the corresponding mode bits in the Operating Mode Register (OMR). If the mode bits are write to 0010 or 1010, respectively, the DSP loads the program RAM from the SCI. Appendix shows the complete bootstrap code. This program (1) configures the SCI, (2) loads the program size, (3) loads the location where the program begins loading in program memory, and (4) loads the program.

First, the SCI Control Register is set to $000302, which enables the transmitter and receiver and configures the SCI for 10 bits asynchronous with one start bit, 8 data bits, one stop bit, and no parity. Next, the SCI Clock Control Register is set to $00C000, which configures the SCI to use external receive and transmit clocks from the SCLK pin input. This external clock must be 16 times the desired serial data rate.

The next step is to receive the program size and then the starting address to load the program. These two numbers are three bytes each loaded least significant byte first. Each byte is echoed back as it is received. After both numbers are loaded, the program size is in A0 and the starting address is in A1.

The program is then loaded one byte at a time, least significant byte first. After the program is loaded, the operating mode is set to zero, the CCR is cleared, and the DSP begins execution with the first instruction loaded

8.5Exceptions

The SCI can cause five different exceptions in the DSP, discussed here from the highest to the lowest priority:

1.SCI receive data with exception status occurs when the receive data register is full with a receiver error (parity, framing, or overrun error). To clear the pending interrupt, read the SCI status register; then read SRX. Use a long interrupt service routine to handle the error condition. This interrupt is enabled by SCR[16] (REIE).

2.SCI receive data occurs when the receive data register is full. Read SRX to clear the pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. This interrupt is enabled by SCR[11] (RIE).

3.SCI transmit data occurs when the transmit data register is empty. Write STX to clear the pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. This interrupt is enabled by SCR[12] (TIE).

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DSP56301 User’s Manual

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Motorola DSP56301 user manual Exceptions, Bootstrap Loading Through the SCI Boot Mode 2 or a
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.