Central Processor Unit (CPU) Registers

Table 4-3.Status Register Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11–10

S[1–0]

0

Scaling Mode

 

 

 

 

 

 

 

Specify the scaling to be performed in the Data ALU shifter/limiter and the

 

 

 

rounding position in the Data ALU MAC unit. The Shifter/limiter Scaling

 

 

 

mode affects data read from the A or B accumulator registers out to the

 

 

 

X-data bus (XDB) and Y-data bus (YDB). Different scaling modes can be

 

 

 

used with the same program code to allow dynamic scaling. One

 

 

 

application of dynamic scaling is to facilitate block floating-point arithmetic.

 

 

 

The scaling mode also affects the MAC rounding position to maintain

 

 

 

proper rounding when different portions of the accumulator registers are

 

 

 

read out to the XDB and YDB. Scaling mode bits are cleared at the start of

 

 

 

a long Interrupt Service Routine and during a hardware reset.

 

 

 

 

 

 

 

 

 

 

 

 

S1

 

S0

Scaling

Rounding Bit

SEquation

 

 

 

 

Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

No scaling

23

S = (A46 XOR A45)

 

 

 

 

 

 

 

 

OR (B46 XOR B45)

 

 

 

 

 

 

 

 

OR S (previous)

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

Scale down

24

S = (A47 XOR A46)

 

 

 

 

 

 

 

 

OR (B47 XOR B46)

 

 

 

 

 

 

 

 

OR S (previous)

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

Scale up

22

S = (A45 XOR A44)

 

 

 

 

 

 

 

 

OR (B45 XOR B44)

 

 

 

 

 

 

 

 

OR S (previous)

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

Reserved

—

S undefined

 

 

 

 

 

 

 

 

9–8

I[1–0]

11

Interrupt Mask

 

 

 

 

 

 

Reflect the current Interrupt Priority Level (IPL) of the processor and

 

 

 

indicate the IPL needed for an interrupt source to interrupt the processor.

 

 

 

The current IPL of the processor can be changed under software control.

 

 

 

The interrupt mask bits are set during hardware reset, but not during

 

 

 

software reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Priority

 

I1

I0

Exceptions

Exceptions Masked

 

 

 

 

Permitted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Lowest

 

0

0

IPL 0, 1, 2, 3

None

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

IPL 1, 2, 3

IPL 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

IPL 2, 3

IPL 0, 1

 

 

 

 

 

 

 

 

 

 

 

 

Highest

 

1

1

IPL 3

IPL 0, 1, 2

 

 

 

 

 

 

 

 

 

7

S

0

Scaling

 

 

 

 

 

 

 

Set when a result moves from accumulator A or B to the XDB or YDB buses

 

 

 

(during an accumulator to memory or accumulator to register move) and

 

 

 

remains set until explicitly cleared; that is, the S bit is a sticky bit. The

 

 

 

logical equations of this bit are dependent on the Scaling mode. The scaling

 

 

 

bit is set if the absolute value in the accumulator, before scaling, is > 0.25 or

 

 

 

< 0.75.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4-10

DSP56301 User’s Manual

Page 83 Page 85
Page 84
Image 84
Motorola DSP56301 user manual Scaling Mode, Scaling Rounding Bit SEquation Mode, Interrupt Mask
Page 83 Page 85

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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