Overview | Motorola DSP56301 specification

Overview

Table 6-2.HI32 Features in PCI Mode and Universal Bus Mode (Continued)

Feature	PCI Mode	Universal Bus Mode


Output Data	24-bit words to 32-bit words:	24-bit words to 16-bit words (two most significant
Alignment	ν Left aligned and zero filled	bytes, two least significant bytes)
	ν Right aligned and zero extended
	ν Right aligned and sign extended

Data	ν Up to 33 Mword/sec zero wait-state data	ν Data transfers at three clock cycles per
Tramsfer	transfers (with a 33 MHz PCI clock and a	transfer (that is, 22 Mword/sec for a 66 MHz
Speed	DSP clock (CLKOUT) frequency of 66 MHz	DSP clock (CLKOUT)), when operating
	or more)	synchronously with an DSP56300
	ν True 32-bit input and output data transfers	core-based DSP host (two wait states per
	(32-bit PCI bus data to two DSP56300 core	access)
	16-bit words, and vice versa)	ν High speed (fast peripheral) DSP56300
	ν Bursts of up to 16384 32-bit words when	core DMA transfers (two core clock cycles
	accessed as a memory-mapped target	per DMA transfer)
	ν Bursts of up to sixty-four 32-bit words or
	unlimited length (as master)
	ν High speed (fast peripheral) DSP56300
	core DMA transfers (two core clock cycles
	per DMA transfer)

Interrupts	ν Software-driven PCI Interrupt Requests	ν Interrupt requests: hardware driven
Interrupts	ν Software-driven PCI Interrupt Requests	ν Interrupt requests: hardware driven	(HIRQ)
	(Interrupt A)	and software driven (HINTA)
	ν Vectored DSP56300 core interrupts;	ν Vectored DSP56300 core interrupts;
	separately for receive, transmit, transaction	separately for receive and transmit events
	termination, error events, and host	and host commands
	commands

Voltage	Both 3.3 V and 5 V PCI signalling environments	An external data buffer may be needed for drive
		and voltage level compatibility with the external
		bus (for example, the ISA bus requires buffering)

System	ν Memory-space and configuration	ν Self-Configuration mode for initializing the
	transactions as a target; memory-space,	configuration registers in a system without
	I/O-space, and configuration transactions	an external system configurator
	as an initiator
	ν Exclusive (locked) accesses
	ν Self-Configuration mode for initializing the
	configuration registers in a system without
	an external system configurator
	ν Address insertion in the data written to the
	HI32
	ν Parity generation, detection, and reporting
	ν System error generation and reporting

6.2Overview

Figure 6-1shows the two banks of registers in the HI32, DSP-side and host-side. The DSP56300 core can access the DSP-side registers, which are listed in Table 6-9,HI32 Programming Model, DSP Side , on page 6-22.The host-side registers, which are accessed by the host bus, are listed in Table 6-17,HI32 Programming Model, Host-Side Registers , on page 6-44.

6-4	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Overview

Models: DSP56301

Table 6-2.HI32 Features in PCI Mode and Universal Bus Mode (Continued)

Feature

PCI Mode

Universal Bus Mode

Speed

Interrupts

System

6.2Overview

DSP56301 specifications