Motorola DSP56301 Bus Request Host Transfer Acknowledge, Hreq is deasserted in the same PCI, Hstr

Host Interface (HI32)

Table 2-12.Host Port Pins (HI32) (Continued)

Signal		PCI			Universal Bus Mode
Name
					Enhanced Universal Bus Mode				GPIO
HP27				HTA					disconnected
	HREQ
	Bus Request			Host Transfer Acknowledge
	Tri-state, Output pin.			Tri-state, Output pin.
	Indicates to the arbiter that the HI32			For high speed data transfer between the
	requires use of the bus.			HI32 and an external host when the host uses
	HREQ is deasserted in the same PCI		a non-interrupt driven handshake mechanism.
	clock that the HI32 asserts HFRAME.			If the HI32 deasserts HTA at the beginning of
	As during the STOP reset HREQ is			the host access, the host should extend the
	high impedance; an external pull-up			access as long as HTA is deasserted. The
	should be connected if it is connected			polarity of the HTA pin is controlled by HTAP
	to the PCI bus arbiter.			in the DCTR.
				The HTA pin is asserted if:
				ν during a data read valid data is present
					on HD23-HD0 (HRRQ=1 in the HSTR).
				ν during a data write it indicates the HI32
					is ready to accept data (HTRQ=1 in the
					HSTR).
				ν during a vector write it indicates the
					HI32 is ready to accept a new host
					command (HC=0 in the HCVR).
HP28									disconnected
	HSERR			HIRQ
	Host System Error			Host Interrupt Request
	Open drain output pin1.			Output pin1.
	Reports address parity errors and			Used by the HI32 to request service from the
	other errors where the result will be			host processor. HIRQ may be connected to
	catastrophic. Asserted for a single			an interrupt request pin of a host processor, a
	PCI clock by the HI32.			transfer request of a DMA controller or a
				control input of external circuitry.
				HIRQ	is initially asserted by the HI32 when an
				interrupt request is enabled (TREQ=1 or
				RREQ=1) and the corresponding data path is
				ready for a data transfer.
				If the HIRH bit in the DCTR is cleared:				HIRQ
				assertion is a pulse with a width controlled by
				the CLAT register.
				If HIRH is set:		HIRQ	is deasserted at the
				beginning of a corresponding host data
				access (read or write), or masked (by
				TREQ=0 or RREQ=0) or disabled (DMAE=1).
				HIRQ is asserted again after the host access
				(regardless of the HIRH value), if enabled and
				the corresponding data path is ready for a
				data transfer. The HIRQ drive (driven or open
				drain) is controlled by the HIRD bit in the
				DCTR.

Signals/Connections 2-19