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Motorola DSP56301 user manual DSP-To-Host Data Path

Models: DSP56301

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Data Transfer Paths

In PCI mode data transfers in which the HI32 is the target (DCTR[HM] = $1) with HCTR[HTF]≠$0, the host-to-DSP data path is a six word deep, 24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core reads 24-bit words from the DRXR. In Universal Bus mode data transfers, the host-to-DSP data path is a five word deep, 24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core reads 24-bit words from the DRXR.

Note: To guarantee proper HI32 operation, the DMA should service the HI32 under the following restrictions:

—Two DMA channels should not service the DRXR FIFO if master and slave data is mixed there.

—The DMA data transfers should not be concurrent with the DSP56300 core data transfers to/from the same HI32 data FIFO.

6.3.2DSP-To-Host Data Path

In PCI mode data transfers in which the HI32 is the master (DCTR[HM] = $1) with DPMC[FC]≠$0, the master DSP-to-host data path (DTXM-HRXM) is an eight word deep FIFO. The DSP56300 core writes to the DSP side of the FIFO (DTXM). The data is output to the bus from the host side (HRXM). In PCI mode data transfers in which the HI32 is the master (DCTR[HM] = $1) with DPMC[FC] = $0, the master DSP-to-host data path is a FIFO four words deep and 32 bits wide. The DSP56300 core writes 24-bit words to the DTXM. Each word written by the DSP56300 core contains 16-bits of significant data, right aligned, the most significant byte is not transmitted. The first word written by the DSP56300 core contains the two least significant bytes of the 32-bit word to be output from the HRXM. The second word written by the DSP56300 core contains the two most significant bytes of the 32-bit word output from the HRXM. Each time a 32-bit word is output from the HRXM, the 32-bits of significant data located in two words written to the DTXM are output.

In PCI mode data transfers in which the HI32 is the target (DCTR[HM] = $1) with HCTR[HRF]≠$0 and in Universal Bus mode data transfers, the slave DSP-to-host data path (DTXS-HRXS) is a six word deep FIFO. The DSP56300 core writes 24-bit words to the DTXS. The data is output, a word at a time, to the bus from the HRXS.

In PCI mode data transfers in which the HI32 is the target (DCTR[HM] = $1) with HCTR[HRF] = $0, the slave DSP-to-host data path is a three word deep, 32-bit wide FIFO. The DSP56300 core writes 24-bit words to the DTXS. Each word written by the DSP56300 core contains 16-bits of significant data, right aligned, the most significant byte is not transmitted. The first word written by the DSP56300 core contains the two least significant bytes of the 32-bit word to be output from the HRXS. The second word written by the DSP56300 core contains the two most significant bytes of the 32-bit word output from the

Host Interface (HI32)

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Motorola DSP56301 user manual DSP-To-Host Data Path
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.