Motorola DSP56301 instruction

Features

Table 6-1.HI32 Features, Core-Side and Host-Side (Continued)

Feature

Core-Side Interface

Host-Side Interface

Handshaking

ν Software polled

Universal Bus mode:

Protocols

ν Interrupt driven (fast or long)

ν Software Polled

ν Direct Memory Access (up to six

ν Interrupt Driven—Data Request (HIRQ

DSP56300 core DMA channels)

pin) and Interrupt A (HINTA pin)

ν Data Acknowledge (HTA pin)

ν Direct Memory Access (External

DMA—HDRQ and HDAK pins)

PCI mode:

ν Software polled (PCI Interrupt

(HINTA

pin))

ν Data Acknowledge

and

(HTRDY

HIRDY

pins)

ν Bus Arbitration

and

(HREQ

HGNT)

GPIO

24 I/O pins (data and pin direction are

programmable)

Self

Indirect write-only access of DSP56300 core to

Configuration

the HI32 configuration registers

Instructions

Memory-mapped registers allow standard

MOVE instruction for data transfers between the

DSP56301 and external hosts; special MOVEP

instruction provides I/O service capability using

fast interrupts and faster execution with fewer

instruction words

Address

ν PCI Mode: 32-bit internal address

Decoding

decoding

ν Universal Bus mode: 11-bit (12 with

HAEN) internal address decoding

Data Fetch

In HI32 (slave) to host data transfers: fetch and

Types

pre-fetch

Semaphores

Flags for HI32 allocation in a multi-host system

Table 6-2.HI32 Features in PCI Mode and Universal Bus Mode

Feature

PCI Mode

Universal Bus Mode

Operation

Initiator (master) or target (slave)

Slave in many standard bus environments (for

example, ISA bus or DSP56300 core-based DSP

Port A bus)

Word Size

8,16, 24, and 32 bits (as defined by the

8,16, and 24 bits wide.

HBE[3–0]

lines)

Input Data

32-bit words to 24 bit words:

16-bit words to 24-bit words

Alignment

ν Three MSBs

ν Left aligned and zero filled

ν Three LSBs

ν Right aligned and zero extended

ν Right aligned and sign extended

Host Interface (HI32)

6-3

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual HI32 Features in PCI Mode and Universal Bus Mode

Models: DSP56301

Table 6-1.HI32 Features, Core-Side and Host-Side (Continued)

Protocols

HIRDY

GPIO

Instructions

Table 6-2.HI32 Features in PCI Mode and Universal Bus Mode

Feature

PCI Mode

Universal Bus Mode

Operation

Alignment

Host Interface (HI32)

DSP56301 specifications