HI32 DSP-Side Programming Model

Table 6-12.DSP PCI Master Control Register (DMPC) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

 

Description

 

 

 

 

 

 

 

 

 

23–22

FC[1–0]

0

DPMC[FC] = $1 or $2

The three least significant PCI data bytes from

Cont.

Cont.

 

 

the HAD[23–0] pins are transferred to the

 

 

 

 

DRXR to be read by the DSP56300 core.

 

 

 

 

 

 

 

 

DPMC[FC] = $3

The three most significant PCI data bytes from

 

 

 

 

the HAD[31–8] pins are transferred to the

 

 

 

 

DRXR to be read by the DSP56300 core.

 

 

 

 

 

21–16

BL[5–0]

0

PCI Data Burst Length

 

 

 

Control the PCI data burst length. The value of the BL[5–0] bits is the

 

 

 

desired number of accesses in the burst, minus one. In PCI mode

 

 

 

(DCTR[HM] = $1), when the DSP56300 core writes to the DPAR, the

 

 

 

master access counter is initialized with the value of BL[5–0]. The

 

 

 

burst length can be programmed from 1 (BL = $00) to 64 (BL = $3F)

 

 

 

accesses. If the master access counter is enabled (MACE = 1 in the

 

 

 

DPCR) and the HI32 is the active PCI master, the value of the counter

 

 

 

decrements after each data cycle in which data is transferred (that is,

 

 

 

a data phase) until the counter value reaches $00. Then the HI32 PCI

 

 

 

master executes one more data phases and terminates the

 

 

 

transaction. A transaction can be terminated before the counter

 

 

 

reaches $00—for example, via a target-initiated transaction

 

 

 

termination, the bus grant is taken, or the DSP56300 core writes a

 

 

 

value of one to MTT. The value of the counter at the end of a

 

 

 

transaction is indicated by the RDC[5–0] bits in the DSP PCI Status

 

 

 

Register (DPSR).

 

 

 

 

 

15–0

AR[31–16]

0

DSP PCI Transaction Address (High)

 

 

 

The two most significant bytes of the 32-bit PCI transaction address.

 

 

 

The two least significant bytes reside in the DPAR (see Section

 

 

 

6.7.4, DSP PCI Address Register (DPAR), on page 6-33). In PCI

 

 

 

mode (DCTR[HM] = $1),when the DSP56300 core writes to the

 

 

 

DPAR, the PCI ownership is requested. When the request is granted,

 

 

 

the HI32 initiates a PCI transaction. The full 32-bit address

 

 

 

(AR[31–16] from the DPMC and AR[15–0] from the DPAR) is driven

 

 

 

to the HAD[31–0] pins during the PCI address phase.

 

 

 

 

 

6-32

DSP56301 User’s Manual

Page 149 Page 151
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Motorola DSP56301 user manual PCI Data Burst Length, DSP PCI Transaction Address High
Page 149 Page 151

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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