Host-Side Programming Model

6.8.7Device ID/Vendor ID Configuration Register (CDID/CVID)

r

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DID15

DID14

DID13

DID12

DID11

DID10

DID9

DID8

DID7

DID6

DID5

DID4

DID3

DID2

DID1

DID0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VID15

VID14

VID13

VID12

VID11

VID10

VID9

VID8

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6-16.Device/Vendor ID Configuration Register (CDID/CVID)

A PCI-standard 32-bit read-only register mapped into the PCI configuration space in PCI mode or in mode 0 (DCTR[HM] = $1 or $0). CDID/CVID is accessed if a configuration read command is in progress and the PCI address is $00. The DID[15–0] bits identify the DSP. The VID[15–0] bits identify the manufacturer of the DSP. The contents of CDID/CVID are hardwired and are unaffected by any type of reset. The host processor can access CDID/CVID only when the HI32 is in PCI mode (DCTR[HM]$1).

Table 6-25.Device ID/Vendor ID Configuration Register (CDID/CVID) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

 

 

 

 

 

 

 

 

31–16

DID[15–0]

Hardwired

Device ID

 

 

 

$1801 = DSP56301

 

 

 

 

15–0

VIV[15–0]

Hardwired

Vendor ID

 

 

 

$1057

 

 

 

 

6.8.8Status/Command Configuration Register (CSTR/CCMR)

r

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DPE

SSE

RMA

RTA

STA

DST1

DST0

DPR

FBBC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SERE WCC PERR

BM

MSE

Not implemented, read as zero, should be written as zero

Reserved, read as zero and should be written as zero

Figure 6-17.Status/Command Configuration Register (CSTR/CCMR)

A PCI-standard 32-bit read/write register mapped into the PCI configuration space in PCI mode or in mode 0 (DCTR[HM] = $1 or $0). CSTR/CCMR is accessed if a configuration

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DSP56301 User’s Manual

Page 182
Image 182
Motorola DSP56301 Device ID/Vendor ID Configuration Register CDID/CVID, Status/Command Configuration Register CSTR/CCMR

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.