SCI Programming Model

As noted in Section 8.6.1, the SCI can be configured to operate in a single Synchronous mode or one of five Asynchronous modes. Synchronous mode requires that the TX and RX clocks use the same source, but that source may be the internal SCI clock if the SCI is configured as a master device or an external clock if the SCI is configured as a slave device. Asynchronous modes may use clocks from the same source (internal or external) or different sources for the TX clock and the RX clock.

For synchronous operation, the SCI uses a clock that is equal to the two times the desired bit rate (designated as the 2 × clock) for both internal and external clock sources. It must use the same source for both the TX and RX clock. The internal clock is used if the SCI is the master device and the external clock is used if the SCI is the slave device, as noted above. The clock is gated and limited to a maximum frequency equal to one eighth of the DSP core operating frequency (that is, 12.5 MHz for a DSP core frequency of 100 MHz).

For asynchronous operation, the SCI can use the internal and external clocks in any combination as the source clocks for the TX clock and RX clock. If an external clock is used for the SCLK input, it must be sixteen times the desired bit rate (designated as the 16 × clock), as indicated in Figure 8-6. When the internal clock is used to supply a clock to an external device, the clock can use the actual bit rate (designated as the 1 × clock) or the 16 × clock rate, as determined by the COD bit. The output clock is continuous.

Select 8-or 9-bit Words

 

Idle Line

0

1

2

3

4

5

6

7

8

 

 

 

 

RX, TX Data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(SSFTD = 0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Start

 

 

 

 

 

 

 

 

 

Stop

Start

x1 Clock

x16 Clock (SCKP = 0)

Figure 8-6.16 x Serial Clock

When SCKP is cleared, the transmitted data on the TXD signal changes on the negative edge of the serial clock and is stable on the positive edge. When SCKP is set, the data changes on the positive edge and is stable on the negative edge. The received data on the RXD signal is sampled on the positive edge (if SCKP = 0) or on the negative edge (if SCKP = 1) of the serial clock.

Serial Communication Interface (SCI)

8-21

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Motorola DSP56301 user manual RX, TX Data Ssftd =, X1 Clock X16 Clock Sckp =
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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