Timer Prescaler Load, Register Tplr | Motorola DSP56301 specs

Triple Timer Module Programming Model

23	0	Timer Prescaler Load
		Timer Prescaler Load
		Register (TPLR)
		TPLR = $FFFF83

23	0

23 22 21 20 19 18 17 16

TCF TOF

15	14	13	12	11	10	9	8
PCE		DO	DI	DIR		TRM	INV

7	6	5	4	3	2	1	0

TC3	TC2	TC1	TC0		TCIE	TOIE	TE

23							0

Timer Prescaler Count Register (TPCR)

TPLR = $FFFF82

Timer Control/Status Register (TCSR)

TCSR0 = $FFFF8F

TCSR1 = $FFFF8B

TCSR2 = $FFFF87

Timer Load

TLR0 = $FFFF8E

TLR1 = $FFFF8A

TLR2 = $FFFF86

23	0	Timer Compare
		Register (TCPR)
		TCPR0 = $FFFF8D
		TCPR0 = $FFFF8D
		TCPR1 = $FFFF89
23	0	TCPR2 = $FFFF85
23	0	Timer Count
		Timer Count
		Register (TCR)
		TCR0 = $FFFF8C
		TCR1 = $FFFF88
		TCR2 = $FFFF84

Reserved bit. Read as 0. Write with 0 for future compatibility

Figure 9-20.Timer Module Programmer’s Model

9-26	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 Timer Prescaler Load, Register Tplr, 23 22 21 20 19 18 17, Tplr = $FFFF83

Models: DSP56301