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Motorola DSP56301 user manual Word Select, WDS1 WDS0, Mode Word Formats

Models: DSP56301

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SCI Programming Model

Table 8-2.SCI Control Register (SCR) Bit Definitions (Continued)

Bit

Bit Name

Reset

 

 

 

Description

Number

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2–0

WDS[2–0]

0

Word Select

 

 

 

 

 

 

Select the format of transmitted and received data. Asynchronous modes are

 

 

 

compatible with most UART-type serial devices, and they support standard RS-232

 

 

 

communication links. Multidrop Asynchronous mode is compatible with the MC68681

 

 

 

DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface. Synchronous

 

 

 

data mode is essentially a high-speed shift register for I/O expansion and stream-mode

 

 

 

channel interfaces. You can synchronize data by using a gated transmit and receive

 

 

 

clock compatible with the Intel 8051 serial interface mode 0. When odd parity is

 

 

 

selected, the transmitter counts the number of ones in the data word. If the total is not

 

 

 

an odd number, the parity bit is set, thus producing an odd number. If the receiver

 

 

 

counts an even number of ones, an error in transmission has occurred. When even

 

 

 

parity is selected, an even number must result from the calculation performed at both

 

 

 

ends of the line, or an error in transmission has occurred.

 

 

 

 

 

 

 

 

 

 

 

WDS2

WDS1

WDS0

Mode

Word Formats

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

8-Bit Synchronous Data (shift register mode)

 

 

 

 

 

 

 

 

 

 

 

0

0

1

1

Reserved

 

 

 

 

 

 

 

 

 

 

 

0

1

0

2

10-Bit Asynchronous (1 start, 8 data, 1 stop)

 

 

 

 

 

 

 

 

 

 

 

1

1

1

3

Reserved

 

 

 

 

 

 

 

 

 

 

 

1

0

0

4

11-Bit Asynchronous

 

 

 

 

 

 

 

(1 start, 8 data, 1 even parity, 1 stop)

 

 

 

 

 

 

 

 

 

 

 

1

0

1

5

11-Bit Asynchronous

 

 

 

 

 

 

 

(1 start, 8 data, 1 odd parity, 1 stop)

 

 

 

 

 

 

 

 

 

 

 

1

1

0

6

11-Bit Multidrop Asynchronous

 

 

 

 

 

 

 

(1 start, 8 data, 1 data type, 1 stop)

 

 

 

 

 

 

 

 

 

 

 

0

1

1

7

Reserved

 

 

 

 

 

 

 

 

8-16

DSP56301 User’s Manual

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Image 252
Motorola DSP56301 user manual Word Select, WDS1 WDS0, Mode Word Formats
Page 251 Page 253

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.