Host-Side Programming Model, Memory Register

Host-Side Programming Model

6.8Host-Side Programming Model

The HI32 appears to the host processor as a bank of registers, listed in Table 6-17.

Table 6-17.HI32 Programming Model, Host-Side Registers

X Memory Register	Register	Mode	Page
Address	Register	Mode	Page
Address


	Host Interface Control Register (HCTR)	UBM	page 48
		PCI

	Host Interface Status Register (HSTR)	UBM	page 57
		PCI

	Host Command Vector Register (HCVR)	UBM	page 59
		PCI

	Host Master Receive Data Register (HRXM)	PCI	page 61

	Host Slave Receive Data Register (HRXS)	UBM	page 61
		PCI

	Host Transmit Data Register (HTXR)	UBM	page 62
		PCI

	Device ID/Vendor ID Configuration Register (CDID/CVID)	PCI	page 67

	Status/Command Configuration Register (CSTR/CCMR)	PCI	page 64

	Class Code/Revision ID Configuration Register	PCI	page 67
	(CCCR/CRID)

	Header Type/Latency Timer Configuration Register	UBM	page 68
	Cache Line Size Configuration Register	PCI
	(CHTY/CLAT/CCLS)

	Memory Space Base Address Configuration Register	UBM	page 70
	(CBMA)	PCI

	Subsystem ID and Subsystem Vendor ID Configuration	PCI	page 71
	Register (CSID)

	Interrupt Line-Interrupt Signal Configuration Register (CILP)	PCI	page 73

Note: As the PCI master, the HI32 uses the HRXM to output data, and the host bus cannot access this register.

In the Universal Bus modes:

νThe HI32 occupies eight words in the host processor address space. The host processor cannot access the PCI configuration registers (CDID/CVID, CSTR/CCMR, CCCR/CRID, CHTY/CLAT, CBMA, CSID, and CILP) in the Universal Bus modes. However, it can configure these registers in Self-Configuration mode.

νBecause of the fast DSP56300 core interrupt response, most host microprocessors can read or write data at their maximum programmed non-DMA instruction rate without testing the handshake flags for each transfer. If the full interrupt driven handshake is not needed, the high-speed data transfer between the host and the HI32 can be supported with only the host data strobe/acknowledge handshake mechanism. DMA

6-44	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 Host-Side Programming Model, 17.HI32 Programming Model, Host-Side Registers

Models: DSP56301

6.8Host-Side Programming Model

Table 6-17.HI32 Programming Model, Host-Side Registers

X Memory Register

Mode

DSP56301 specifications