DSP PCI Control Register Dpcr, Host Flags

HI32 DSP-Side Programming Model

Table 6-10.DSP Control Register (DCTR) Bit Definitions (Continued)

Bit Number	Bit Name	Reset	Mode	Description
Bit Number	Bit Name	Value	Mode	Description
		Value


5–3	HF[5–3]	0	UB/PCI	Host Flags
				General-purpose flags for DSP-to-host communication. The DSP56300
				core can set or clear these bits. HF[5–3] are visible to the external host
				in the HSTR. There are six host flags: three by which the host signals
				the DSP56300 core (HF[2–0]) and three by which the DSP56300 core
				signals the host processor (HF[5–3]). The host flags do not cause
				interrupts; they must be polled to determine whether they have
				changed. These flags can be used individually or as encoded triads.

2	SRIE	0	UB/PCI	Slave Receive Interrupt Enable
				Enables a DSP56300 core interrupt request when the slave receive
				data request (SRRQ) status bit in the DSR is set. When SRIE is
				cleared, SRRQ interrupt requests are disabled. When SRIE is set, a
				slave receive data interrupt request is generated if SRRQ is set.

1	STIE	0	UB/PCI	Slave Transmit Interrupt Enable
				Enables a DSP56300 core interrupt request when the slave transmit
				data request (STRQ) status bit in the DSR is set. When STIE is cleared,
				STRQ interrupt requests are disabled. When STIE is set, a slave
				transmit data interrupt request is generated if STRQ is set.

0	HCIE	0	UB/PCI	Host Command Interrupt Enable
				Enables a vectored core interrupt request when the DSR[HCP] is set.
				When HCIE is cleared, HCP interrupt requests are disabled. When
				HCIE and DSR[HCP] are both set, a host command interrupt request is
				generated. The starting address of this interrupt is determined by the
				host vector HV[6–0] in the Host Command Vector Register (HCVR).
				When the host non-maskable interrupt (HNMI) bit is set in the Host
				Command Vector Register (HCVR), HCIE is ignored, and an interrupt is
				generated if HCP is set, regardless of HCIE.

6.7.2DSP PCI Control Register (DPCR)

The DPCR is a 24-bit read/write control register by which the DSP56300 core controls the HI32 PCI interrupts and interface logic. The host processor cannot access the DPCR. The bit manipulation instructions are useful for accessing individual bits in the DPCR.

23	22	21	20	19	18	17	16

		IAE	RBLE	MWSD	MACE		SERF
15	14	13	12	11	10	9	8

MTT	CLRT		TCIE			TTIE
7	6	5	4	3	2	1	0

TAIE		PEIE	MAIE		MRIE	MTIE

Reserved. Write to 0 for future compatibility

Figure 6-6.DSP PCI Control Register (DPCR)

6-26	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 DSP PCI Control Register Dpcr, Host Flags, Slave Receive Interrupt Enable

Models: DSP56301

Table 6-10.DSP Control Register (DCTR) Bit Definitions (Continued)

Mode

Host Flags

Slave Receive Interrupt Enable

Slave Transmit Interrupt Enable

Host Command Interrupt Enable

6.7.2DSP PCI Control Register (DPCR)

Figure 6-6.DSP PCI Control Register (DPCR)

DSP56301 specifications