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Motorola DSP56301 Enhanced Synchronous Serial Interface, Hardware Reset, Host Interrupt a

Models: DSP56301

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Enhanced Synchronous Serial Interface 0

Table 2-12.Host Port Pins (HI32) (Continued)

Signal

 

 

 

PCI

Universal Bus Mode

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

Enhanced Universal Bus Mode

GPIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HP49

 

 

 

 

HRST

 

 

HRST

 

 

 

 

 

Hardware Reset

Hardware Reset

 

 

 

Input pin.

Schmitt-trigger input pin.

 

 

 

Forces the HI32 PCI sequencer to the

Forces the HI32 to its initial state. All pins are

 

 

 

initial state. All pins are forced to the

forced to the disconnected state. The polarity

 

 

 

disconnected state.

of the HRST pin is controlled by HRSP bit in

 

 

 

HRST is asynchronous to HCLK.

the DCTR.

 

 

 

 

 

 

 

 

HP50

 

 

 

 

 

 

 

 

 

HINTA

 

 

 

 

 

 

 

Host Interrupt A

 

 

 

 

 

 

Active low, open drain output pin(3).

 

 

 

 

 

 

Used by the HI32 to request service from the host processor.

HINTA

can connect to an interrupt request

 

 

pin of a host processor, a control input of external circuitry, or be used as a general-purpose open-drain

 

 

output.

 

 

 

 

 

 

HINTA is asserted by the HI32 when the DSP56300 core sets DCTR[HINT].

 

 

 

HINTA is released (high impedance) when the DSP56300 core clears DCTR[HINT].

 

 

 

HINTA is asynchronous to HCLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes: 1. This list does not include VCC and Ground supply pins.

2. The GPIO pin is controlled by the corresponding bits in the GPIO data (DATH) and GPIO direction (DIRH) registers.

3. Open-drain output pin is driven, when asserted, by the HI32. When deasserted the pin is released (high impedance). This enables using a multi-slave configuration. An external pull-up must connect externally for proper operation.

4. Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a time. The agent that drives this pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a sustained tri-state signal any sooner that one clock after the previous owner tri-states it. A pull-up resistor is required to sustain the inactive state until another agent drives it.

5. All pins except PCVL are 5 V tolerant.

2.8Enhanced Synchronous Serial Interface 0

Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard CODECs, other DSPs, microprocessors, and peripherals that implement the Motorola serial peripheral interface (SPI). All ESSI pins are 5V tolerant.

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DSP56301 User’s Manual

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Motorola DSP56301 user manual Enhanced Synchronous Serial Interface, Hardware Reset, Host Interrupt a
Page 51 Page 53

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.