Asynchronous 8-1

Synchronous 8-1programming model 8-9

data registers 8-22Receive Data (RXD) 8-4recover synchronization 8-2reset 8-5

RXD, TXD, SCLK 8-3

SCI Clock Control Register (SCCR) 8-7,8-8,8-9,8-19

bit definitions 8-19Clock Divider (CD) 8-20Clock Out Divider (COD) 8-19Clock Prescaler (SCP) 8-19programming sheet B-36

Receive Clock Mode Source (RCM) 8-19Transmit Clock Source (TCM) 8-19

SCI Control Register (SCR) 8-7,8-8,8-9,8-12bit defintions 8-12

Idle Line Interrupt Enable (ILIE) 8-13programming sheet B-35

Receive with Exception Interrupt Enable (REIE) 8-12

Receiver Enable (RE) 8-14

Receiver Wakeup Enable (RWU) 8-15SCI Clock Polarity (SCKP) 8-12

SCI Receive Interrupt Enable (RIE) 8-13SCI Shift Direction (SSFTD) 8-15

SCI Transmit Interrupt Enable (TIE) 8-13Send Break (SBK) 8-15

Timer Interrupt Enable (TMIE) 8-13Timer Interrupt Rate (STIR) 8-12Transmitter Enable (TE) 8-14Wakeup Mode Select (WAKE) 8-15Wired-OR Mode Select (WOMS) 8-14Word Select (WDS) 8-16

SCI Receive Data Register (SRX) 8-9,8-22SCI Status Register (SSR) 8-9,8-17

bit definitions 8-17

Framing Error Flag (FE) 8-17Idle Line Flag (IDLE) 8-18Overrun Error Flag (OR) 8-18Parity Error (PE) 8-17

Receive Data Register Full (RDRF) 8-18Received Bit 8 (R8) 8-17

Transmit Data Register Empty (TDRE) 8-18Transmitter Empty (TRNE) 8-18

SCI Transmit Data Address Register (STXA) 8-9SCI Transmit Data Register (STX) 8-9

select wakeup on idle line mode 8-15Serial Clock (SCLK) 8-4,8-21state after reset 8-5

Synchronous mode 8-2transmission priority

preamble, break, and data 8-7transmit and receive shift registers 8-2Transmit Data (TXD) 8-4

Transmit Data Register (STX or STXA) 8-22Transmit Data Register (STX) 8-23Wired-OR mode 8-3

Serial Control 0 (SC00 and SC10) signals 7-4Serial Control 1 (SC01 and SC11) signals 7-4Serial Control 2 (SC02 and SC12) signals 7-6Serial Control Direction 0 (SCD0) bit 7-23Serial Control Direction 1 (SCD1) bit 7-23Serial Control Direction 2 (SCD2) bit 7-23Serial Input Flag 0 (IF0) bit 7-4,7-29

Serial Input Flag 1 (IF1) bit 7-29

Serial Output Flag (OF0–OF1) bits 7-18Serial Output Flag 0 (OF0) bit 7-4,7-23Serial Output Flag 1 (OF1) bit 7-23Serial Receive Data (SRD) signal 7-3Serial Transmit Data (STD) signal 7-3setting timer operating mode 9-4

Shift Direction (SHFD) bit 7-22Signaled System Error (SSE) bit 6-65Signalled Target Abort (STA) bit 6-65signals

by function 2-1functional grouping 2-2

Sixteen-bit Arithmetic Mode (SA) bit 4-8Sixteen-bit Compatibility (SC) mode 3-6Sixteen-bit Compatibility (SC) mode bit 3-7,4-9Size register (SZ) 1-8

Slave Fetch Type (SFT) 6-52

Slave Receive Data Request (SRRQ) bit 6-36Slave Receive Interrupt Enable (SRIE) bit 6-26Slave Transmit Data Request (STRQ) bit 6-37Slave Transmit Interrupt Enable (STIE) bit 6-26SRAM support 1-5

Stack Counter register (SC) 1-8

Stack Extension Enable (SEN) bit 4-12

Stack Extension Overflow Flag (EOV) bit 4-13Stack Extension Underflow Flag (EUN) bit 4-13Stack Extension Wrap Flag (WRP) bit 4-12Stack Extension XY Select (XYS) bit 4-13Stack Pointer (SP) 1-8

start-up procedure location 4-2Status Register (SR) 1-8,4-7

bit definitions 4-7

Condition Code Register (CCR) 4-7Carry (C) 4-11

Extension (E) 4-11Limit (L) 4-11Negative (N) 4-11Overflow (V) 4-11Scaling (S) 4-10Unnormalized (U) 4-11

Index-13

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Motorola DSP56301 user manual Index-13
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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