HI32 DSP-Side Programming Model | Motorola DSP56301 manual

HI32 DSP-Side Programming Model

6.7HI32 DSP-Side Programming Model

The DSP56300 core views the HI32 as a memory-mapped peripheral occupying eleven 24-bit words in data memory space. Table 6-9shows the HI32 DSP-side programming model.

Table 6-9.HI32 Programming Model, DSP Side

X Memory Register Address	Mode	Register	Page


X:FFFFC5	PCI	DSP Control Register (DCTR)	page 23
	Universal Bus

X:FFFFC6	PCI only	DSP PCI Control Register (DPCR)	page 26

X:FFFFC7	PCI	DSP PCI Master Control Register (DPMC)	page 30
	Self-Configuration

X:FFFFC8	PCI	DSP PCI Address Register (DPAR)	page 33
	Self-Configuration

X:FFFFC9	PCI	DSP Status Register (DSR)	page 35
	Universal Bus

X:FFFFCA	PCI only	DSP PCI Status Register (DPSR)	page 38

X:FFFFCB	PCI	DSP Receive Data FIFO (DRXR)	page 41
	Universal Bus

X:FFFFCC	PCI	DSP Master Transmit Data FIFO (DTXM)	page 42
	Universal Bus

X:FFFFCD	PCI	DSP Slave Transmit Data FIFO (DTXS)	page 42
	Universal Bus

X:FFFFCE	Universal Bus	DSP Host Port GPIO Direction Register	page 43
	(DCTR[HM] = $2)	(DIRH)
	GPIO

X:FFFFCF	Universal Bus	DSP Host Port GPIO Data Register	page 43
	(DCTR[HM] = $2)	(DATH)
	GPIO

The separate host-to-DSP and DSP-to-host data paths are FIFOs through which the HI32 and the host processor transfer data efficiently and at high speeds. Memory mapping allows the DSP56300 core to transfer data with the HI32 registers using standard instructions and addressing modes. In addition, the MOVEP instruction allows HI32-to-memory and memory-to-HI32 data transfers without the use of an intermediate register. The DSP56300 core can access the HI32 using either standard polling, interrupt, or DMA techniques. The general-purpose DMA channels in the DSP56300 core can be programmed to transfer data between the HI32 data FIFOs and other DMA accessible resources at maximum throughput without DSP56300 core intervention. This section describes the purpose and operation of each bit in the HI32 registers that are visible to the DSP56300 core. The HI32 host-side programming model is described in Section 6.8, Host-Side Programming Model, on page 6-44.

6-22	DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual HI32 DSP-Side Programming Model, HI32 Programming Model, DSP Side

Models: DSP56301

6.7HI32 DSP-Side Programming Model

Table 6-9.HI32 Programming Model, DSP Side

X Memory Register Address

Mode

DSP56301 specifications