Index-10 DSP56301 User’s Manual | Motorola instruction

Memory Base Address Low (PM[15–4]) 6-71Memory Space (MS[1–0]) 6-71

Memory Space Indicator (MSI) 6-71Pre-Fetch (PF) 6-71

Universal Bus Mode Base Address (GB[10–3]) 6-70Memory Space Indicator (MSI) 6-71

Memory Switch (MS) bit 3-7Memory Switch mode 3-2

Xdata Memory 3-3

Ydata memory 3-4

Memory Switch Mode (MS) bit 4-14MIN_GNT (MG[7–0]) bits 6-73MODA– MODD pins 4-2,8-8mode control 2-9

Mode Register (MR) 4-7Do Loop Flag (LF) 4-8

Double-Precision Multiply Mode (DM) 4-9Interrupt Mask (I) 4-10

Scaling (S) Mode 4-10

Sixteen-bit Compatibility (SC) mode 4-9Mode Select (MOD) bit 7-21

Mode Select A (MODA) 2-9

Mode Select B (MODB) 2-9

Mode Select C (MODC) 2-9

Mode Select D (MODD) 2-9modulo adder 1-7

MOVE instruction 6-42MOVEP instruction 6-22Multidrop mode 8-2Multiplication Factor (MF) bits 4-21Multiplier-Accumulator (MAC) 1-6,1-7

Negative (N) bit 4-11

Network mode 7-8

Non-Maskable Interrupt (NMI) 2-9

off-chip memory 1-5,3-1offset adder 1-7

on-chip DRAM controller 1-5

On-Chip Emulation (OnCE) module 1-5,1-9interface 2-29

on-chip memory 1-5,1-10On-Demand mode 7-10,7-15operating mode definitions 4-3

Operating Mode Register (OMR) 1-8,4-6,4-12,6-72Address Attribute Priority Disable (APD) 4-13Address Trace Enable (ATE) 4-13Asynchronous Bus Arbitration Enable (ABE) 4-13Bus Release Timing (BRT) 4-14

Cache Burst Mode Enable (BE) 4-14

Chip Operating Mode (MD–MA) 4-15COM byte 4-12

Core-DMA Priority (CDP) 4-14EOM byte 4-12

External Bus Disable (EBD) 4-15

Memory Switch Mode (MS) 4-14programming sheet B-14

SCS byte 4-12

Stack Extension Enable (SEN) 4-12

Stack Extension Overflow Flag (EOV) 4-13Stack Extension Underflow Flag (EUN) 4-13Stack Extension Wrap Flag (WRP) 4-12Stack Extension XY Select (XYS) 4-13Stop Delay Mode (SD) 4-15

TA Synchronize Select (TAS) 4-14operating modes 4-2

HI32 6-12Overflow (V) bit 4-11Overrun Error Flag (OR) bit 8-18

Parity Error (PE) bit 8-17

Parity Error Interrupt Enable (PEIE) 6-29Parity Error Response (PERR) bit 6-66PCI Address Parity Error (APER) bit 6-40PCI bus command 6-45

PCI Bus Command (C[3–0]) bits 6-34PCI Bus Master Enable (BM) bit 6-66PCI Byte Enables (BE[3–0] ) bits 6-33PCI Data Burst Length (BL[5–0]) bits 6-32PCI Data Parity Error (DPER) 6-40

PCI Device Base Class (BC[7–0]) 6-67

PCI Device Program Interface (P[17–10]) 6-67PCI Device Sub-Class (SC[7–0]) bits 6-67

PCI Host Data Transfer Complete (HDTC) bit 6-39PCI host-to-DSP data transfers 6-45

PCI idle state 6-13PCI master

active 6-13

PCI Master Abort (MAB) 6-40

PCI Master Address Request (MARQ) bit 6-40

PCI Master Receive Data Request (MRRQ) bit 6-41PCI Master Transmit Data Request (MTRQ) 6-41PCI Master Wait States (MWS) bit 6-41

PCI Memory Address Space 6-47

PCI Memory Space Enable (MSE) 6-66PCI Mode 6-63

PCI mode 6-13,6-45,6-63,6-64memory space transactions 6-57

PCI Target Abort (TAB) 6-40

PCI Target Disconnect (TDIS) bit 6-40PCI Target Retry (TRTY) bit 6-39

PCI Time Out Termination (TO) bit 6-39

Index-10

DSP56301 User’s Manual

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola user manual Index-10 DSP56301 User’s Manual

Models: DSP56301

Index-10

DSP56301 User’s Manual

DSP56301 specifications