Host-Side Programming Model

νIn a 16-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HRF]≠$0), the HD[15–0] pins are driven with the two least significant bytes of the HSTR in a read access.

νIn PCI mode (DCTR[HM] = $1) memory space transactions, the HSTR is accessed if the PCI address is HI32_base_address: $014.

νIn a Universal Bus mode (DCTR[HM] = $2 or $3), the HSTR is accessed if the HA[10–3] value matches the HI32 base address (see Section 6.8.11, Memory Space Base Address Configuration Register (CBMA), on page 6-70)and the HA[2–0] value is $5.

Table 6-23.Host Interface Status Register (HSTR) Bit Definitions

Bit

Bit Name

Reset

Mode

 

 

 

Description

Number

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31–8

 

0

 

Reserved. Write to 0 for future compatibility.

 

 

 

 

 

 

 

 

 

7

HREQ

0

UBM

Host Request

 

 

 

 

 

 

PCI

Set and cleared as follows. The personal software reset clears HREQ.

 

 

 

 

 

 

 

 

 

 

 

 

TREQ

 

RREQ

 

HREQ

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

cleared

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

set if HRRQ = 1

 

 

 

 

 

 

 

 

otherwise cleared

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

set if HTRQ = 1

 

 

 

 

 

 

 

 

otherwise cleared

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

set if HTRQ = 1 or HRRQ = 1

 

 

 

 

 

 

 

 

otherwise cleared

 

 

 

 

 

 

 

 

 

6

HINT

0

UBM

Host interrupt A

 

 

 

 

 

 

PCI

Reflects the status of the HINT bit in the DSP Control Register (DCTR)

 

 

 

 

and the HINTA pin. HINT is set if the host interrupt A bit is set in the

 

 

 

 

DCTR and the HINTA pin is driven low. HINT is cleared if the host

 

 

 

 

interrupt A is cleared in the DCTR, and the HINTA pin is driven low.

 

 

 

 

 

 

 

 

5–3

HF[5–3]

0

UBM

Host Flags

 

 

 

 

 

 

PCI

Indicate the state of host flags HF[5–3], respectively, in the DSP Control

 

 

 

 

Register (DCTR) on the DSP side. Only the DSP56300 core can

 

 

 

 

change HF[5–3].

 

 

 

 

 

 

 

 

 

 

 

 

Host Interface (HI32)

6-57

Page 174 Page 176
Page 175
Image 175
Motorola DSP56301 Host Interface Status Register Hstr Bit Definitions, Host Request, Host interrupt a, Treq Rreq Hreq
Page 174 Page 176

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
Top Page Image Contents