Motorola DSP56301 user manual Dram Control Register DCR $FFFFFA Read/Write

Programming Sheets

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Sheet 2 of 3

Bus Interface Unit

NOTE: All DCR bits are read/write control bits.

Refresh Prescaler, Bit 23		Bus Software Triggered
0 = Prescaler bypassed		Refresh, Bit 14
		0 = Refresh complete/reset
1 = Divide-by-64 prescaler used		1 = Software triggered refresh request					Bus Row Out-of-Page
							Wait States, Bits 3–2
	Refresh Request Rate, Bits 22–15		Bus Refresh				00 = 4 wait states
	These read/write control bits define		Enable, Bit 13				01 = 8 wait states
	the refresh request rate. The bits		0 = Disable				10 = 11 wait states
			1 = Enable
	specify a divide from 1–256						11 = 15 wait states
	(BRF[7–0] = $00–$FF). A refresh
	request is generated every time			Bus Mastership
	the refresh counter reaches zero,			Enable, Bit 12				Bus In-Page
	if the refresh counter is enabled			0 = Disable				Wait States, Bits 1–0
	(i.e., BREN = 1).			1 = Enable				00 = 1 wait state
								01 = 2 wait states
					Bus Page Logic
								10 = 3 wait states
					Enable, Bit 11
								11 = 4 wait states
					0 = Disable
					1 = Enable
						Bus DRAM Page Size, Bits 9–8
						00 = 9-bit column width, 512
						01 = 10-bit column width, 1 K
						10 = 11-bit column width, 2 K
						11 = 12-bit column width, 4 K

23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRP				BRF[7–0]					BSTR	BREN	BME	BPLE	*0	BPS[1–0]		*0	*0	*0	*0	BRW[1–0]		BCW[1–0]
DRAM Control Register (DCR)										X:$FFFFFA Read/Write
Reset = $000000																	* = Reserved, Program as 0

Figure B-7.DRAM Control Register (DCR)

Programming Reference B-19