Memory Base Address Low Hardwired to zeros

			Host-Side Programming Model

Table 6-29.Memory Space Base Address Configuration Register (CBMA)
		Bit Definitions (Continued)

Bit Number	Bit Name	Reset Value	Description


15–4	PM[15–4]	0	Memory Base Address Low (Hardwired to zeros)

3	PF	0 (Hardwired)	Pre-Fetch (Hardwired to zero)
			Indicates whether the data is pre-fetchable. PF is hardwired to zero and
			is unaffected by any type of reset.

2–1	MS[1 –0]	0 (Hardwired)	Memory Space (Hardwired to zeros)
			Specifies that the CBMA register is 32 bits wide and mapping can be
			done anywhere in the 32-bit memory space. MS1 and MS0 are
			hardwired to zero and are unaffected by any type of reset.

0	MSI	0 (Hardwired)	Memory Space Indicator (Hardwired to zero)
			Specifies that the CBMA register maps the HI32 into the PCI memory
			space. MSI is hardwired to zero and is unaffected by any type of reset.

6.8.12Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

SID15	SID14	SID13	SID12	SID11	SID10	SID9	SID8	SID7	SID6	SID5	SID4	SID3	SID2	SID1	SID0

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

SVID	SVID	SVID	SVID	SVID	SVID	SVID	SVID	SVID	SVID	SVID	SVID	SVID	SVID	SVID	SVID
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Figure 6-21.Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)

A PCI-standard read/write register mapped into the PCI configuration space in PCI mode (HM = $1). The CSID register is read if a configuration read command is in progress and the PCI address is $2C. In Self-Configuration mode (HM = $5), the DSP56300 core can indirectly write the CSID (see Section 6.5.5, Self-Configuration Mode (DCTR[HM] = $5), on page 6-16).

The host cannot access the CSID register when the system is not in PCI mode (HM≠$1). This register uniquely identifies the add-in board or subsystem in which the DSP56301 resides. Add-in card vendors can use this mechanism to distinguish their cards from one another even though the cards may have the same DSP56301 on them (and therefore the same Vendor ID and Device ID). Implementation of this register is optional, and an all-zero value indicates that the device (for example, add-in board) does not support subsystem identification. The CSID bits are cleared after power-up. Any reset does not affect the value written to the CSID.

Host Interface (HI32)

6-71

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Memory Space Base Address Configuration Register Cbma

Models: DSP56301

Host-Side Programming Model

Table 6-29.Memory Space Base Address Configuration Register (CBMA)