Host-Side Programming Model

The HTXR receives data from the HI32 data pins via the data transfer format converter (HDTFC). The value of the HCTR[FC] bits or the HCTR[HTF] bits define which bytes of the PCI bus are written to the HTXR and their alignment. (See Table 6-3,HI32 (PCI Master Data Transfer Formats, on page 6-8,Section 6.3.1, Host-to-DSP Data Path, on page 6-6and Table 6-4,Transmit Data Transfer Format, on page 6-9).

When HSTR[HTRQ] is set and TREQ in the HCTR is set:

νThe HSTR[HREQ] status bit is set.

νThe HIRQ pin is asserted, if DMAE is cleared (in the Universal Bus modes).

νThe HDRQ pin is asserted, if DMAE is set (in the Universal Bus modes).

Hardware, software, and personal software resets empty the HTXR (HSTR[HTRQ] is set).

6.8.6.1 PCI Mode (DCTR[HM] = $1)

As the active target in a memory space write transaction, the HTXR is accessed if the PCI address is between HI32_base_address: $01C and HI32_base_address: $FFFC (that is, the host processor views HTXR as a 16377 Dword write-only memory). As the active master, the HTXR is written with all data read from the accessed target. In PCI host-to-DSP data transfers, data is written to the HTXR FIFO in accordance with FC[1–0] or HTF[1–0] bits, regardless of the value of the byte enable pins (HC3/HBE3-HC0/HBE0).

If TWSD is cleared, the HI32 as the selected PCI target (DCTR[HM] = $1) in a write data phase to the HTXR, inserts PCI wait states if the HTXR is full (HTRQ = 0). Wait states are inserted until the data transfers from the HTXR to the DSP side. Up to eight wait states can be inserted before a target-initiated transaction termination (disconnect-C/Retry) is generated.

6.8.6.2 Universal Bus mode (DCTR[HM] = $2 or $3)

The HTXR is accessed if the HA10-HA3 value matches the HI32 base address (see Section 6.8.11, Memory Space Base Address Configuration Register (CBMA), on page 6-70)and the HA[2–0]value is $7. In 24-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HTF = $0), the host processor views the HTXR as a 24-bit write-only register. HD[23– 0] pins are written to all three bytes of the HTXR in a write access. In a 16-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HTF≠$0), the host processor views the HTXR as a 16-bit write-only register. In a write access, the HD[15– 0] pins are written to the two most significant bytes or least significant bytes of the HTXR, as defined by the HCTR[HTF].

In a Universal Bus mode write to the HTXR the HI32 inserts wait states if the HTXR is full (HTRQ = 0). Wait states are inserted until the data is transferred from the HTXR to the DSP side.

Host Interface (HI32)

6-63

Page 180 Page 182
Page 181
Image 181
Motorola DSP56301 user manual PCI Mode Dctrhm = $1, Universal Bus mode Dctrhm = $2 or $3
Page 180 Page 182

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
Top Page Image Contents