Motorola DSP56301 user manual PCI Mode Dctrhm = $1, Universal Bus mode Dctrhm = $2 or $3

Host-Side Programming Model

The HTXR receives data from the HI32 data pins via the data transfer format converter (HDTFC). The value of the HCTR[FC] bits or the HCTR[HTF] bits define which bytes of the PCI bus are written to the HTXR and their alignment. (See Table 6-3,HI32 (PCI Master Data Transfer Formats, on page 6-8,Section 6.3.1, Host-to-DSP Data Path, on page 6-6and Table 6-4,Transmit Data Transfer Format, on page 6-9).

When HSTR[HTRQ] is set and TREQ in the HCTR is set:

νThe HSTR[HREQ] status bit is set.

νThe HIRQ pin is asserted, if DMAE is cleared (in the Universal Bus modes).

νThe HDRQ pin is asserted, if DMAE is set (in the Universal Bus modes).

Hardware, software, and personal software resets empty the HTXR (HSTR[HTRQ] is set).

6.8.6.1 PCI Mode (DCTR[HM] = $1)

As the active target in a memory space write transaction, the HTXR is accessed if the PCI address is between HI32_base_address: $01C and HI32_base_address: $FFFC (that is, the host processor views HTXR as a 16377 Dword write-only memory). As the active master, the HTXR is written with all data read from the accessed target. In PCI host-to-DSP data transfers, data is written to the HTXR FIFO in accordance with FC[1–0] or HTF[1–0] bits, regardless of the value of the byte enable pins (HC3/HBE3-HC0/HBE0).

If TWSD is cleared, the HI32 as the selected PCI target (DCTR[HM] = $1) in a write data phase to the HTXR, inserts PCI wait states if the HTXR is full (HTRQ = 0). Wait states are inserted until the data transfers from the HTXR to the DSP side. Up to eight wait states can be inserted before a target-initiated transaction termination (disconnect-C/Retry) is generated.

6.8.6.2 Universal Bus mode (DCTR[HM] = $2 or $3)

The HTXR is accessed if the HA10-HA3 value matches the HI32 base address (see Section 6.8.11, Memory Space Base Address Configuration Register (CBMA), on page 6-70)and the HA[2–0]value is $7. In 24-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HTF = $0), the host processor views the HTXR as a 24-bit write-only register. HD[23– 0] pins are written to all three bytes of the HTXR in a write access. In a 16-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HTF≠$0), the host processor views the HTXR as a 16-bit write-only register. In a write access, the HD[15– 0] pins are written to the two most significant bytes or least significant bytes of the HTXR, as defined by the HCTR[HTF].

In a Universal Bus mode write to the HTXR the HI32 inserts wait states if the HTXR is full (HTRQ = 0). Wait states are inserted until the data is transferred from the HTXR to the DSP side.

Host Interface (HI32) 6-63