Motorola DSP56301 user manual Index-9

I

I/O space

Xdata memory 3-4

Ydata memory 3-5

Idle Line Flag (IDLE) bit 8-18

Idle Line Interrupt Enable (ILIE) bit 8-13Idle Line Wakeup mode 8-3

illegal PCI events 6-46initialization

system 5-1initializing the timer 9-3input data alignment 6-3

Insert Address Enable (IAE) bit 6-27instruction cache 1-5,3-2

location 3-6

instruction cache controller 1-4internal buses 1-10

internal memory configuration summary 3-6internal program memory 3-1,3-2interrupt 1-8

configuring 4-15source priorities 4-19sources 4-16,4-17table 4-15

table, memory map 4-17trigger mode 4-17vector 4-17

interrupt and mode control 2-1,2-9interrupt control 2-9

Interrupt Line (IL[7–0]) bits 6-73

Interrupt Line-Interrupt Pin Configuration Register (CILP)

Interrupt Line (IL[7–0]) 6-73

Interrupt Pin (IP[7–0]) 6-73

MAX_LAT (ML[7–0]) 6-73

MIN_GNT (MG[7–0]) 6-73Interrupt Mask (I) bits 4-10Interrupt Pin (IP[7–0]) bits 6-73

Interrupt Priority Register Core (IPRC) 4-16IRQD– IRQA Priority and Mode (IDL–IAL) 4-16programming sheet B-15

Interrupt Priority Register Peripherals (IPRP) 4-16ESSI0 Interrupt Priority Level (S0L) 4-16ESSI1 Interrupt Priority Level (S1L) 4-16HI32 Interrupt Priority Level (HPL) 4-16programming sheet B-16

SCI Interrupt Priority Level (SCL) 4-16Timer Interrupt Priority Level (TOL) 4-16

Interrupt Request A (IRQA) 2-9

Interrupt Request B (IRQB) 2-9

Interrupt Request C(IRQC)2-9

Interrupt Request D (IRQD) 2-9Interrupt Service Routine (ISR) 7-9,9-4

interrupt trigger event 7-9interrupts 1-4,5-2,5-3

core

HI32 6-4Inverter (INV) bit 9-30,9-32

IRQD– IRQA Priority and Mode (IDL–IAL) bits 4-16ISA/EISA bus DMA-type accesses 6-15

J

Joint Test Action Group (JTAG) 1-5,1-9,4-35

interface 2-29

JTAG/OnCE Port 2-2

L

Latency Timer (High) (LT[7–0]) 6-69Limit (L) bit 4-11

Literature Distribution Center 1-14Loop Address (LA) register 1-8Loop Counter (LC) register 1-8low-power state 6-13

M

M68HC11 SCI interface 8-16MA–MD bits 4-5

mapping control registers 5-2

Master Access Counter Enable (MACE) 6-28Master Address Interrupt Enable (MAIE) bit 6-30Master Data Transferred (MDT) bit 6-39Master Receive Interrupt Enable (MRIE) bit 6-30Master Transfer Terminate (MTT) bit 6-28Master Transmit Interrupt Enable (MTIE) bit 6-30Master Wait State Disable (MWSD) bit 6-28MAX_LAT (ML[7–0]) bits 6-73

MC68681 DUART 8-16memory

allocation switching 3-2configuration 3-5configuration summary 3-6dynamic switching 3-5expansion 3-1

maps 3-7on-chip 1-10

Memory Base Address High/Low (PM[31–16]) bits 6-70Memory Base Address Low (PM[15–4]) 6-71memory expansion port 1-5

memory space X I/O 5-2

Memory Space (MS[1–0]) bits 6-71

Memory Space Base Address Configuration Register (CBMA)

Memory Base Address High/Low (PM[31–16] 6-70

Index-9