Index-9

I/O space

Xdata memory 3-4

Ydata memory 3-5

Idle Line Flag (IDLE) bit 8-18

Idle Line Interrupt Enable (ILIE) bit 8-13Idle Line Wakeup mode 8-3

illegal PCI events 6-46initialization

system 5-1initializing the timer 9-3input data alignment 6-3

Insert Address Enable (IAE) bit 6-27instruction cache 1-5,3-2

location 3-6

instruction cache controller 1-4internal buses 1-10

internal memory configuration summary 3-6internal program memory 3-1,3-2interrupt 1-8

configuring 4-15source priorities 4-19sources 4-16,4-17table 4-15

table, memory map 4-17trigger mode 4-17vector 4-17

interrupt and mode control 2-1,2-9interrupt control 2-9

Interrupt Line (IL[7–0]) bits 6-73

Interrupt Line-Interrupt Pin Configuration Register (CILP)

Interrupt Line (IL[7–0]) 6-73

Interrupt Pin (IP[7–0]) 6-73

MAX_LAT (ML[7–0]) 6-73

MIN_GNT (MG[7–0]) 6-73Interrupt Mask (I) bits 4-10Interrupt Pin (IP[7–0]) bits 6-73

Interrupt Priority Register Core (IPRC) 4-16IRQD– IRQA Priority and Mode (IDL–IAL) 4-16programming sheet B-15

Interrupt Priority Register Peripherals (IPRP) 4-16ESSI0 Interrupt Priority Level (S0L) 4-16ESSI1 Interrupt Priority Level (S1L) 4-16HI32 Interrupt Priority Level (HPL) 4-16programming sheet B-16

SCI Interrupt Priority Level (SCL) 4-16Timer Interrupt Priority Level (TOL) 4-16

Interrupt Request A (IRQA) 2-9

Interrupt Request B (IRQB) 2-9

Interrupt Request C(IRQC)2-9

Interrupt Request D (IRQD) 2-9Interrupt Service Routine (ISR) 7-9,9-4

interrupt trigger event 7-9interrupts 1-4,5-2,5-3

core

HI32 6-4Inverter (INV) bit 9-30,9-32

IRQD– IRQA Priority and Mode (IDL–IAL) bits 4-16ISA/EISA bus DMA-type accesses 6-15

Joint Test Action Group (JTAG) 1-5,1-9,4-35

interface 2-29

JTAG/OnCE Port 2-2

Latency Timer (High) (LT[7–0]) 6-69Limit (L) bit 4-11

Literature Distribution Center 1-14Loop Address (LA) register 1-8Loop Counter (LC) register 1-8low-power state 6-13

M68HC11 SCI interface 8-16MA–MD bits 4-5

mapping control registers 5-2

Master Access Counter Enable (MACE) 6-28Master Address Interrupt Enable (MAIE) bit 6-30Master Data Transferred (MDT) bit 6-39Master Receive Interrupt Enable (MRIE) bit 6-30Master Transfer Terminate (MTT) bit 6-28Master Transmit Interrupt Enable (MTIE) bit 6-30Master Wait State Disable (MWSD) bit 6-28MAX_LAT (ML[7–0]) bits 6-73

MC68681 DUART 8-16memory

allocation switching 3-2configuration 3-5configuration summary 3-6dynamic switching 3-5expansion 3-1

maps 3-7on-chip 1-10

Memory Base Address High/Low (PM[31–16]) bits 6-70Memory Base Address Low (PM[15–4]) 6-71memory expansion port 1-5

memory space X I/O 5-2

Memory Space (MS[1–0]) bits 6-71

Memory Space Base Address Configuration Register (CBMA)

Memory Base Address High/Low (PM[31–16] 6-70

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.

Motorola DSP56301 user manual Index-9

Models: DSP56301

Index-9

DSP56301 specifications