Operating Modes

Table 4-2.Operating Mode Definitions

Mode

Description

0Expanded mode—Bypasses the bootstrap ROM. The DSP56301 begins fetching instructions, starting at $C00000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected (default).

1Bootstrap from byte-widememory—Loads a program memory segment from consecutive byte-wide P memory locations, starting at P:$D00000 (bits 7-0). The memory is selected by the Address Attribute AA1 and is accessed with 31 wait states. The EPROM bootstrap code expects first to read 3 bytes specifying the number of program words, then 3 bytes specifying the address to start loading the program words, and then 3 bytes for each program word to be loaded. The number of words, the starting address, and the program words are read least significant byte first followed by the middle and then the most significant byte. The program concatenates consecutive three byte sequences into 24-bit words and stores them in contiguous PRAM memory locations starting at the specified address. After the program words are read, program execution starts from the same address where loading started.

2Bootstrap through SCI—The hardware reset vector is located at address $FF0000 in the bootstrap ROM. The program bootstraps through the SCI. The bootstrap program sets the SCI to operate in 10-bit asynchronous mode, with 1 start bit, 8 data bits, 1 stop bit, and no parity. Data is received in this order: start bit, 8 data bits (LSB first), and one stop bit. Data is aligned in the SCI receive data register with the LSB of the least significant byte of the received data appearing at Bit 0.The user must provide an external clock source with a frequency at least 16 times the transmission data rate. Each byte received by the SCI is echoed back through the SCI transmitter to the external transmitter. The boot program concatenates every three bytes read from the SCI into a 24-bit wide DSP56301 word.

Note: DSP CLKOUT rate must be at least 64 times the data transmission rate.

3Host bootstrap in DSP-to-DSPmode—The hardware reset vector is located at address $FF0000 in the bootstrap ROM. The program bootstraps through the HI32 in UB mode, double strobe, HTA pin active low. The DSP56301 is written with 24-bit-wide words.

Note: DSP CLKOUT rate must be at least three times the data transfer rate.

4Bootstrap from SPI-compatible Serial EEPROM through the SCI— The hardware reset vector is at address $FF0000 in the bootstrap ROM. The program bootstraps through the HI32 in standard PCI slave configuration. The DSP56301 is written with 24-bit-wide words encapsulated in 32-bit wide PCI transfers.

Note: DSP CLKOUT rate must be 5/3 of the PCI clock.

5Host bootstrap 16-bit wide ISA slave glueless interface in UB mode—Loads the program memory from the Host Interface programmed to operate in the Universal Bus mode supporting ISA (slave) glueless connection. Using Self-Configuration mode, the base address in the CBMA is initially written with $2F, corresponding to an ISA HTXR address of $2FE (Serial Port 2 Modem Status read-only register). The HI32 bootstrap code expects to read 32 consecutive times the magic number $0037. Subsequently, the bootstrap code expects to read a 16-bit word that is the designated ISA Port Address; this address is written into the CBMA. The HOST Processor must poll for the Host Interface to be reconfigured. This must be done by reading the HSTR and verifying that the value $0013 is read. Then the host processor starts writing data to the Host Interface. The HI32 bootstrap code expects to read a 24-bit word first that specifies the number of program words, followed by a 24-bit word specifying the address from which to start loading the program words, followed by a 24-bit word for each program word to be loaded. The program words are stored in contiguous PRAM memory beginning at the specified starting address. After reading the program words, program execution starts from the address where loading started.

Note: DSP CLKOUT rate must be at least three times the data transfer rate.

Core Configuration

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Motorola DSP56301 user manual Operating Mode Definitions, Mode Description
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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