Motorola DSP56301 user manual Power Inputs, Ground Signals

Power

2.1Power

	Table 2-2.Power Inputs
Power	Description
Name
VCCP	PLL Power—V CC dedicated for PLL use. The voltage should be well-regulated and the input should be provided
	with an extremely low impedance path to the VCC power rail.
VCCQL	Quiet Core (Low) Power—An isolated power for the core processing logic. This input must be isolated
	externally from all other chip power inputs. The user must provide adequate external decoupling capacitors.
VCCQH	Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other
	chip power inputs. The user must provide adequate decoupling capacitors.
VCCA	Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied
	externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
VCCD	Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally
	to all other chip power inputs. The user must provide adequate external decoupling capacitors.
VCCC	Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all
	other chip power inputs. The user must provide adequate external decoupling capacitors.
VCCH	Host Power—An isolated power for the HI32 I/O drivers. This input must be tied externally to all other chip
	power inputs. The user must provide adequate external decoupling capacitors.
VCCS	ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be
	tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

2.2Ground

	Table 2-3.Ground Signals
Ground	Description
Name
GNDP	PLL Ground— GND dedicated for PLL use. The connection should be provided with an extremely
	low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 μF capacitor located as close as
	possible to the chip package.
GNDP1	PLL Ground 1—GND dedicated for PLL use. The connection should be provided with an extremely
	low-impedance path to ground.
GNDQ	Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied externally to
	all other chip ground connections. The user must provide adequate external decoupling capacitors.
GNDA	Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This connection must be
	tied externally to all other chip ground connections. The user must provide adequate external decoupling
	capacitors.
GNDD	Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection must be tied
	externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
GNDN	Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be tied
	externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
GNDH	Host Ground—An isolated ground for the HI32 I/O drivers. This connection must be tied externally to all other
	chip ground connections. The user must provide adequate external decoupling capacitors.
GNDS	ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This connection
	must be tied externally to all other chip ground connections. The user must provide adequate external
	decoupling capacitors.

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