Bus Interface Unit (BIU) Registers

4.6.3Address Attribute Registers (AAR[0–3])

The Address Attribute Registers (AAR[0–3]) are read/write registers that control the activity of the AA0/RAS0AA3/RAS3 pins. The associated AAn/RASn pin is asserted if the address defined by the BAC bits in the associated AAR matches the exact number of external address bits defined by the BNC bits, and the external address space (X data, Y data, or program) is enabled by the AAR. Figure 4-8shows an AAR register; Table 4-11lists the bit definitions.

Note: The DSP56301 does not support address multiplexing.

23

22

21

20

19

18

17

16

15

14

13

 

12

 

 

 

 

BAC11

BAC10

BAC9

BAC8

BAC7

BAC6

BAC5

BAC4

BAC3

BAC2

BAC1

BAC0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address to Compare

11

10

9

8

7

6

5

4

 

3

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BNC3

BNC2

BNC1

BNC0

 

BPAC

 

 

BYEN

BXEN

BPEN

BAAP

BAT1

BAT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

External Access Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AA pin polarity

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program space Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X data space Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y data space Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Packing Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Number of Address bit to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

compare

Reserved Bit. Write to zero for future compatibility.

Figure 4-8.Address Attribute Registers (AAR[0–3]) (X:$FFFFF9–$FFFFF6)

Table 4-11.Address Attribute Registers (AAR[0–3]) Bit Definitions

Bit

Bit Name

Reset

Description

Number

Value

 

 

 

 

 

 

 

 

 

 

 

 

23–12

BAC[11–0]

0

Bus Address to Compare

 

 

 

Read/write control bits that define the upper 12 bits of the 24-bit address with which to

 

 

 

 

 

 

 

 

 

compare the external address to determine whether to assert the corresponding AA/RAS

 

 

 

 

signal. This is also true of 16-bit compatibility mode. The BNC[3–0] bits define the number

 

 

 

of address bits to compare.

 

 

 

 

11–8

BNC[3–0]

0

Bus Number of Address Bits to Compare

 

 

 

Specify the number of bits (from the BAC bits) that are compared to the external address.

 

 

 

The BAC bits are always compared with the Most Significant Portion of the external

 

 

 

address (for example, if BNC[3–0] = 0011, then the BAC[11–9] bits are compared to the 3

 

 

 

MSBs of the external address). If no bits are specified (that is, BNC[3–0] = 0000), the AA

 

 

 

signal is activated for the entire 16 M-word space identified by the space enable bits

 

 

 

(BPEN, BXEN, BYEN), but only when the address is external to the internal memory map.

 

 

 

The combinations BNC[3–0] = 1111, 1110, 1101 are reserved.

 

 

 

 

 

 

Core Configuration

4-27

Page 101
Image 101
Motorola DSP56301 Address Attribute Registers AAR0-3, Bus Address to Compare, Bus Number of Address Bits to Compare

DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.