M_SCTE

EQU

9

; SCI Transmitter Enable

M_TDRE

EQU

1

; Transmit Data Register Empty

M_RDRF

EQU

2

; Receive Data Register Full

M_PCRE

EQU

$FFFF9F

; Port E Control register

M_DCTR

EQU

$FFFFC5

; DSP CONTROL REGISTER (DCTR)

M_DPMC

EQU

$FFFFC7

; DSP PCI MASTER CONTROL REGISTER (DPMC)

M_DPAR

EQU

$FFFFC8

; DSP PCI ADDRESS REGISTER (DPAR)

M_DSR

EQU

$FFFFC9

; DSP STATUS REGISTER (DSR)

M_DRXR

EQU

$FFFFCB

; DSP RECEIVE DATA FIFO (DRXR)

M_AAR1

EQU

$FFFFF8

; Address Attribute Register 1

M_PDRC

EQU

$FFFFBD

;; Port C GPIO Data Register

M_PRRC

EQU

$FFFFBE

;; Port C Direction Register

SCK0

EQU

$3

;; SCK0 is bit #3 as GPIO

 

ORG PL:$ff0000,PL:$ff0000

; bootstrap code starts at $ff0000

START

 

 

 

 

 

clr a #$0a,X0

; clear a and load X0 with constant $0a0000

 

move #$3e,x1

; X1=$3E0000 prepare for UB mode host programming

 

 

 

; HM=$3 (UB)

 

 

 

; HIRD=1 (HIRQ_ pin - drive high enabled)

 

 

 

; HIRH=1 (HIRQ_ pin - handshake enabled)

 

 

 

; HRSP=1 (HRST pin - active low)

 

 

 

; HTAP=0 (HTA pin - active high)

 

 

 

; HDSM=0 (Double-strobe pin mode enabled)

 

movec

omr,a1

 

 

 

and #$f,a

; modd is not don’t care

 

move

a1,n0

 

 

 

move

#TABLE,r0

 

 

TABLE

;; Table is here because it should actuallly start from 1

 

jmp

(r0)+n0

 

 

one

 

 

; Reserved, currently aliased to ’b1001

 

bra

<EPROMLD

; MD:MC:MB:MA=0001 , load from eprom

two

 

 

 

 

 

bra

<SCILD

; MD:MC:MB:MA=0010 , load from SCI

three

 

 

; Reserved, used for burn-in

 

bra

<BURN

; MD:MC:MB:MA=0011 ,burn

four

 

 

 

 

 

bra

<SEREPROM

; MD:MC:MB:MA=0100, Serial EPROM

five

 

 

; Reserved, currently aliased to ’b1101

 

bra

<ISAHOSTLD

; MD:MC:MB:MA=0101, 16 bit UB ISA mode

six

 

 

 

 

 

bra

<UB2HOSTLD

; MD:MC:MB:MA=0110, UB double strobe

seven

 

 

; Reserved, currently aliased to ’b1111

 

bra

<UB1HOSTLD

; MD:MC:MB:MA=0111, UB single strobe

eight

nop

 

 

; external boot

nine

 

 

 

 

 

bra

<EPROMLD

; MD:MC:MB:MA=1001 , load from eprom

ten

 

 

 

 

 

bra

<SCILD

; MD:MC:MB:MA=1010 , load from SCI

eleven

 

 

 

 

 

bra

<UB3HOSTLD

; MD:MC:MB:MA=1011 ,301 to 301 boot

twelve

 

 

 

 

 

bra

<PCIHOSTLD

; MD:MC:MB:MA=1100, PCI 32 bit

thirteen

 

 

 

 

bra

<ISAHOSTLD

; MD:MC:MB:MA=1101, 16 bit UB ISA mode

fourteen

 

 

 

 

bra

<UB2HOSTLD

; MD:MC:MB:MA=1110, UB double strobe

fifteen

 

 

 

 

DSP56301 User’s Manual

A-7

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Motorola DSP56301 user manual Mscte EQU
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DSP56301 specifications

The Motorola DSP56301 is a highly efficient digital signal processor, specifically engineered for real-time audio and speech processing applications. This DSP is part of Motorola's renowned DSP56300 family, which is recognized for its innovative features and outstanding performance in the realm of digital signal processing.

One of the main features of the DSP56301 is its ability to handle complex computations at high speeds. With a maximum clock frequency of 66 MHz, it delivers fast performance, enabling it to process audio signals in real time. The chip is built on a 24-bit architecture, which allows for high-resolution audio processing. This is particularly beneficial in applications such as telecommunications, consumer audio devices, and professional audio equipment, where precision is paramount.

The DSP56301 boasts a comprehensive instruction set that includes efficient mathematical operations, which are essential for digital filters and audio effects processing. One of the key innovations of this device is its dual data path architecture, which permits simultaneous processing of multiple data streams. This feature significantly enhances the device's throughput and responsiveness, making it suitable for demanding applications such as voice recognition and synthesis.

In terms of memory regions, the DSP56301 includes several on-chip memory categories, such as program memory, data memory, and a specialized memory for coefficients. The architecture's support for external memory expansion further increases its versatility, allowing designers to tailor systems to their specific requirements.

The DSP56301 implements advanced features such as a powerful on-chip hardware multiplier and accumulator, simplifying complex mathematical tasks and accelerating the execution of algorithms. Its flexible interrupt system enhances its capability to respond to time-sensitive operations, while the integrated serial ports facilitate efficient data communication with external devices.

Power consumption is also a vital characteristic of the DSP56301. It is designed with energy efficiency in mind, allowing for extended operation in battery-powered devices. The chip’s low power requirements are particularly advantageous in portable audio devices and other applications where energy conservation is crucial.

In conclusion, the Motorola DSP56301 is an exceptional digital signal processor that combines high processing power, flexibility, and efficiency. Its main features, advanced technologies, and robust architecture make it a top choice for developers seeking to create sophisticated audio and signal processing systems. With its enduring legacy in the industry, the DSP56301 continues to be relevant in a variety of modern applications, ensuring it remains a valuable tool for engineers and designers.
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