Status Registers
Overview
Status Byte The Status byte register contains the STB and RQS(MSS) messages as defined in
488.1.The user can read the status byte register using a 488.1 serial poll or the 488.2 *STB? common command. If the user sends a serial poll, bit 6 will respond with Request Service (RSQ). The value of the status byte is not altered by a serial poll.
The *STB? query causes the device to send the contents of the Status Byte Register and the Master Summary Status (MSS) summary message. The *STB? query does not alter the status byte, MSS, or RQS.
Table 4.11 Status Byte Summary Register
Bit | Bit Weight | Bit Name | Description |
0 | 1 | Reserved |
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1 | 2 | Reserved |
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2 | 4 | Error/Event | Set if any errors are present in |
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| Queue (ERR) | the Error/Event queue. |
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3 | 8 | Questionable | Set if any bits are set in the |
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| Status Register | Questionable Status Event |
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| (QSR) | register and the corresponding |
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| bit then the Questionable |
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| Status Enable register is TRUE. |
4 | 16 | Message | MAV is TRUE if the power |
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| Available (MAV) | supply is ready to accept a |
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| request from the controller to |
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| output data. FALSE when the |
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| output queue is empty. |
5 | 32 | Standard Event | A summary of the Standard |
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| Status Bit | Event Status Register. TRUE |
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| Summary (ESB) | with a bit is set in the Standard |
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| Event Status register. |
6 | 64 | Request Service | MSS indicates that the device |
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| (RQS) | has at least one reason for |
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| Master Status | requesting service. |
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| Summary (MSS) |
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7 | 128 | Operation Status | TRUE if a bit is set in the |
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| Register (OSR) | Operation status register and |
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| the corresponding bit in the |
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| Operation Status Enable |
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| register is set. |
Release 2.1 | 79 |