Status Registers

Status Register Commands

To clear the Service Request Enable Register send "*SRE 0." The Power-on Status Clear command also determines if the Service Request Enable Register is cleared at power-on. A cleared register does not allow status information to generate a service request.

E.g.

Sending "*SRE 8" sets bit 3 of the Service Request Enable Register. This will cause the Summary bit of the Questionable Status register (bit 3) in the Status Byte to generate a service request message whenever it gets set.

*SRE <status-enable>, *SRE?

or the multichannel equivalent: STATus<channel>:SREQuest:ENABle <status-enable> STATus<channel>:SREQuest:ENABle?

Parallel Poll Enable Register

Each of the 16 bits in the Parallel Poll Enable register correspond to bits in the Status Byte. Each bit in the Parallel Poll Enable register is ANDed with its corresponding bit in the Status Byte and the resulting bits are ORed together to generate ist.

Therefore using the parallel poll enable register allows any single bit or combination of bits to control the ist message.

The Power-on Status Clear command determines if the Parallel Poll Enable Register is cleared at power-on.

E.g.

Sending "*PRE 8" sets bit 3 of the Parallel Poll Enable Register. This will cause the Summary bit of the Questionable Status register (bit 3) in the Status Byte to generate a TRUE ist message whenever it gets set.

Command: *PRE <status-enable>, *PRE?

Status Byte

The status byte query will return the contents of the status byte register and the MSS (Master Summary Status) message. The response is in the format of a weighted decimal value representing the status byte register and the MSS message (bit 6). Thus, the response to *STB? is identical to the response to a serial poll except that the MSS message appears in bit 5 in place of the RQS message. (See “Status Byte” on page 79 for details.)

*STB?

Release 2.1

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