AMD SC1200 manuals
Computer Equipment > Computer Hardware
When we buy new device such as AMD SC1200 we often through away most of the documentation but the warranty.
Very often issues with AMD SC1200 begin only after the warranty period ends and you may want to find how to repair it or just do some service work.
Even oftener it is hard to remember what does each function in Computer Hardware AMD SC1200 is responsible for and what options to choose for expected result.
Fortunately you can find all manuals for Computer Hardware on our side using links below.
443 pages 3.42 Mb
3 Contents5 List of Figures9 List of Tables13 1.0Overview1.1 General DescriptionFigure 1-1. Block Diagram GX1 Video Processor Core Logic SuperI/O 14 1.2 Features17 2.0Architecture Overview2.1 GX1 Module 22 2.2 Video Processor Module2.2.1 GX1 Module Interface 2.2.2 Video Input Port 2.2.3 Core Logic Module Interface 2.2.4 CRT DAC 2.3 Core Logic Module2.3.1 Other Core Logic Module Interfaces 23 2.4 SuperI/O Module2.5 Clock, Timers, and Reset Logic2.5.1 Reset LogicAMD Geode SC1200/SC1201 Processor Data Book 25 Signal Definitions 32579B 25 3.0Signal DefinitionsTFT/VOP Interface TV Parallel Port/ CRT System Figure 3-1. Signal Groups ACCESS.bus IDE/TFT Memory Video Port AMD Geode SC1200/SC1201 Processor 27 3.1 Ball AssignmentsTable 3-1. Signal Definitions Legend Figure 3-2. BGU481 Ball Assignment DiagramNote: Signal names have been abbreviated in this figure due to space constraints. 28 AMD Geode SC1200/SC1201 Processor71 4.0General Configuration Block89 5.0SuperI/O Module141 6.0Core Logic Module311 7.0Video Processor Module363 8.0Debugging and Monitoring8.1 Testability (JTAG)8.1.1 Mandatory Instruction Support 8.1.2 Optional Instruction Support 8.1.3 JTAG Chain Table 8-1. JTAG Mode Instruction Support 365 9.0Electrical Specifications9.1 General Specifications 371 9.2 DC Characteristics376 9.3 AC CharacteristicsFigure 9-2. General Drive level and Measurement Points Table 9-11. Default Levels for Measurement of Switching Parameters 377 9.3.1 Memory Controller InterfaceFigure 9-3. Memory Controller Drive Level and Measurement Points 378 Table 9-12. Memory Controller Timing Parameters379 Figure 9-4. Memory Controller Output Valid Timing DiagramFigure 9-5. Read Data In Setup and Hold Timing Diagram 9.3.2 Video Port (VP) Interface Figure 9-6. Video Input Port Timing Diagram Table 9-13. Video Input Port Timing Parameters 380 t PCK_FR t tt VFigure 9-7. Video Output Port Timing Diagram Table 9-14. Video Output Port Timing Parameters 381 t VPCK_FR t t VP_V tt382 9.3.3 CRT and TFT InterfaceFigure 9-8. TFT Timing Diagram Table 9-15. TFT Timing Parameters 383 Table 9-16. CRT VESA Compatible DAC (RED, GREEN, and BLUE Outputs)384 9.3.4 TV Interface Table 9-17. TV DAC (4 Outputs: CVBS, SVY/TVR, SVC/TVB, CVBS/TVG)385 9.3.5 ACCESS.bus InterfaceTable 9-18. ACCESS.bus Input Timing Parameters Table 9-19. ACCESS.bus Output Timing Parameters 386 Figure 9-9. ACB Signals: Rising and Falling Timing DiagramFigure 9-10. ACB Start and Stop Condition Timing Diagram Table 9-19. ACCESS.bus Output Timing Parameters (Continued) 387 Figure 9-11. ACB Start Condition TIming DiagramFigure 9-12. ACB Data Bit Timing Diagram 388 9.3.6 PCI BusFigure 9-13. Testing Setup for PCI Slew Rate and Minimum Timing Table 9-20. PCI AC Specifications 389 Figure 9-14. V/I Curves for PCI Output Signals390 Figure 9-15. PCICLK Timing and Measurement PointsTable 9-21. PCI Clock Parameters 391 Figure 9-16. Load Circuits for PCI Maximum Time MeasurementsTable 9-22. PCI Timing Parameters 392 Figure 9-17. PCI Output Timing M easurement ConditionsTable 9-23. Measurement Condition Parameters 393 Figure 9-18. PCI Input Timing Measurement ConditionsFigure 9-19. PCI Reset Timing 394 9.3.7 Sub-ISA InterfaceTable 9-24. Sub-ISA Timing Parameters 395 Table 9-24. Sub-ISA Timing Parameters (Continued)396 Figure 9-20. Sub-ISA Read Operation Timing Diagram397 Figure 9-21. Sub -ISA Write Operation Timing Diagram398 9.3.8 LPC InterfaceFigure 9-22. LPC Output Timing Diagram Figure 9-23. LPC Input Timing Diagram Table 9-25. LPC and SERIRQ 399 9.3.9 IDE Interface TimingFigure 9-24. IDE Reset Timing Diagram Table 9-26. IDE General Timing Parameters 400 Table 9-27. IDE Register Transfer to/from Device Timing Parameters401 Figure 9-25. Register Transfer to/from Device Timing Diagram402 Table 9-28. IDE PIO Data Transfer to/from Device Timing Parameters403 Figure 9-26. PIO Data Transfer to/from Device Timing Diagram404 Table 9-29. IDE Multiword DMA Data Transfer Timing Parameters405 Figure 9-27. Multiword DMA Data Transfer Timing Diagram406 Table 9-30. IDE UltraDMA Data Burst Timing Parameters407 Figure 9-28. Initiating an UltraDMA Data in Burst Timing Diagram408 Figure 9-29. Sustained UltraDMA Data In Burst Timing Diagram409 Figure 9-30. Host Pausing an UltraDMA Data In Burst Timing Diagram410 Figure 9-31. Device Terminating an UltraDMA Data In Burst Timing Diagram411 Figure 9-32. Host Terminating an UltraDMA Data In Burst Timing Diagram412 Figure 9-33. Initiating an UltraDMA Data Out Burst Timing Diagram413 Figure 9-34. Sustained UltraDMA Data Out Burst Timing Diagram414 Figure 9-35. Device Pausing an UltraDMA Data Out Burst Timing Diagram415 Figure 9-36. Host Terminating an UltraDMA Data Out Burst Timing Diagram416 Figure 9-37. Device Terminating an UltraDMA Data Out Burst Timing Diagram417 9.3.10 Universal Serial Bus (USB) Table 9-31. USB Timing Parameters 418 Table 9-31. USB Timing Parameters (Continued)419 Figure 9-38. USB Data Signal Rise and Fall Timing DiagramFigure 9-39. USB Source Differential Data Jitter Timing Diagram 420 Figure 9-40. USB EOP Width Timing DiagramFigure 9-41. USB Receiver Jitter Tolerance Timing Diagram 421 9.3.11 Serial Port (UART)Figure 9-42. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram Table 9-32. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Parameters t 422 9.3.12 Fast IR Port TimingFigure 9-43. Fast IR Timing (MIR and FIR) Diagram Table 9-33. Fast IR Port Timing Parameters 423 9.3.13 Parallel Port TimingFigure 9-44. Standard Parallel Port Typical Data Exchange Timing Diagram Table 9-34. Standard Parallel Port Timing Parameters 424 Figure 9-45. Enhanced Parallel Port Timing DiagramTable 9-35. Enhanced Parallel Port Timing Parameters 425 Figure 9-46. ECP Forward Mode Timing DiagramTable 9-36. ECP Forward Mode Timing Parameters 426 Figure 9-47. ECP Reverse Mode Timing DiagramTable 9-37. ECP Reverse Mode Timing Parameters 427 9.3.14 Audio Interface Timing (AC97)Figure 9-48. AC97 Reset Timing Diagram Figure 9-49. AC97 Sync Timing Diagram Table 9-38. AC Reset Timing Parameters Table 9-39. AC97 Sync Timing Parameters 428 Figure 9-50. AC97 Clocks DiagramTable 9-40. AC97 Clocks Parameters 429 Figure 9-51. AC97 Data TIming DiagramTable 9-41. AC97 I/O Timing Parameters t t 430 Figure 9-52. AC97 Rise and Fall Timing DiagramTable 9-42. AC97 Signal Rise and Fall Timing Parameters 431 Figure 9-53. AC97 Low Power Mode Timing DiagramTable 9-43. AC97 Low Power Mode Timing Parameters 432 9.3.15 Power ManagementFigure 9-54. PWRBTN# Trigger and ONCTL# Timing Diagram Figure 9-55. GPWIO a nd ONCTL# Timing Diagram Table 9-44. PWRBTN# Timing Parameters Table 9-45. Power Management Event (GPWIO) and ONCTL# Tim ing Parameters 433 9.3.16 Power-Up SequencingFigure 9-56. Power-Up Sequencing With PWRBTN# Timing Diagram Table 9-46. Power-Up Sequence Using the Power Button Timing Parameters 434 Figure 9-57. Power-Up Sequencing Without PWRBTN# Timing DiagramTable 9-47. Power-Up Sequence Not Using the Power Button Timing Parameters 435 9.3.17 JTAG InterfaceFigure 9-58. TCK Measurement Points and Timing Diagram Table 9-48. JTAG Timing Parameters 436 Figure 9-59. JTAG Test Timing Diagram 437 10.0Package Specifications10.1 Thermal Characteristics Table 10-1. JC (C/W) Table 10-2. Case-to-Ambient Thermal Resistance Example @ 85C 10.1.1 Heatsink Considerations Figure 10-1. Heatsink Example 438 441 Appendix ASupport Documentation
Also you can find more AMD manuals or manuals for other Computer Equipment.