AMD SC1201, SC1200 manual PIC Interrupt Mapping, Programmable Interrupt Controller, Master

Core Logic Module 32579B

6.2.6.3Programmable Interrupt Controller

The Core Logic module contains two 8259A-equivalent programmable interrupt controllers, with eight interrupt request lines each, for a total of 16 interrupts. The PIC devices support all x86 modes of operation except Special Fully Nested mode. The two controllers are cascaded inter- nally, and two of the interrupt request inputs are connected to the internal circuitry. This allows a total of 13 externally available interrupt requests. See Figure 6-9.

Each Core Logic IRQ signal can be individually selected to as edge- or level-sensitive. The four PCI interrupt signals may be routed internally to any PIC IRQ.

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	Table 6-4. PIC Interrupt Mapping
Master
IRQ	Mapping
IRQ0	Connected to the OUT0 (system timer) of
	the internal 8254 PIT.
IRQ2	Connected to the slave’s INTR for a cas-
	caded configuration.
IRQ8#	Connected to internal RTC.
IRQ13	Connected to the FPU interface of the
	GX1 module.
IRQ15	Interrupts available to other functions

8254 Timer 0	IRQ0
	IRQ1
	IRQ2
	IRQ3
	IRQ4
	IRQ5
	IRQ6
	IRQ7

IR0

IR1

IR2

IR3

IR4

IR5

IR6

IR7

Internal

INTR

IRQ14

IRQ12

IRQ11

IRQ10

IRQ9

IRQ7

IRQ6

RTC_IRQ#	IRQ8#	IR0
	IRQ9
		IR1
	IRQ10
		IR2
	IRQ11
		IR3
	IRQ12
		IR4
	IRQ13
FPU		IR5
	IRQ14
		IR6
	IRQ15
		IR7

Figure 6-8. PIC Interrupt Controllers

Three interrupts are available externally depending upon selected ball multiplexing:

1)IRQ15 (muxed with GPIO11+RI2#),

2)IRQ14 (muxed with TFTD1), and

3)IRQ9 (muxed with IDE_DATA6)

More of the IRQs are available through the use of SERIRQ (muxed with GPIO39) function. See Table 6-4.

IRQ5

IRQ4

IRQ3

IRQ1

The Core Logic module allows PCI interrupt signals INTA#, INTB#, INTC# (muxed with GPIO19+IOCHRDY) and INTD# (muxed with IDE_DATA7) to be routed internally to any IRQ signal. The routing can be modified through Core Logic module’s configuration registers. If this is done, the IRQ input must be configured to be level- rather than edge- sensitive. IRQ inputs may be individually programmed to be level-sensitive with the Interrupt Sensitivity configuration registers at I/O address space 4D0h and 4D1h. PCI inter- rupt configuration is discussed in further detail in “PCI Compatible Interrupts” on page 156.

AMD Geode™ SC1200/SC1201 Processor Data Book 155