SC1200/SC1201 Processor Memory Controller Registers | AMD specs

32579BArchitecture Overview

Table 2-1. SC1200/SC1201 Processor Memory Controller Register Summary

GX_BASE+	Width
Memory Offset	(Bits)	Type	Name/Function	Reset Value

8400h-8403h	32	R/W	MC_MEM_CNTRL1. Memory Controller Control Register 1	248C0040h

8404h-8407h	32	R/W	MC_MEM_CNTRL2. Memory Controller Control Register 2	00000801h

8408h-840Bh	32	R/W	MC_BANK_CFG. Memory Controller Bank Configuration	41104110h

840Ch-840Fh	32	R/W	MC_SYNC_TIM1. Memory Controller Synchronous Timing	2A733225h
			Register 1

8414h-8417h	32	R/W	MC_GBASE_ADD. Memory Controller Graphics Base	00000000h
			Address Register

8418h-841Bh	32	R/W	MC_DR_ADD. Memory Controller Dirty RAM Address	00000000h
			Register

841Ch-841Fh	32	R/W	MC_DR_ACC. Memory Controller Dirty RAM Access	0000000xh
			Register

Table 2-2. SC1200/SC1201 Processor Memory Controller Registers

Bit	Description

GX_BASE+ 8400h-8403h		MC_MEM_CNTRL1 (R/W)	Reset Value: 248C0040h

31:30	MDCTL (MD[63:0] Drive Strength). 11 is strongest, 00 is weakest.

29	RSVD (Reserved). Write as 0.

28:27	MABACTL (MA[12:0] and BA[1:0] Drive Strength). 11 is strongest, 00 is weakest.

26	RSVD (Reserved). Write as 0.

25:24	MEMCTL (RASA#, CASA#, WEA#, CS[1:0]#, CKEA, DQM[7:0] Drive Strength). 11 is strongest, 00 is weakest.

23:22	RSVD (Reserved). Write as 0.

21	RSVD (Reserved). Must be written as 0. Wait state on the X-Bus x_data during read cycles - for debug only.

20:18	SDCLKRATE (SDRAM Clock Ratio). Selects SDRAM clock ratio.
	000: Reserved	100: ÷ 3.5
	001: ÷ 2	101: ÷ 4
	010: ÷ 2.5	110: ÷ 4.5
	011: ÷ 3 (Default)	111: ÷ 5
	Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.

17	SDCLKSTRT (Start SDCLK). Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of this reg-
	ister).
	0: Clear.
	1: Enable.
	This bit must transition from zero (written to zero) to one (written to one) in order to start SDCLK or to change the shift value.

16:8	RFSHRATE (Refresh Interval). This field determines the number of processor core clocks multiplied by 64 between refresh
	cycles to the DRAM. By default, the refresh interval is 00h. Refresh is turned off by default.

7:6	RFSHSTAG (Refresh Staggering). This field determines number of clocks between the RFSH commands to each of the
	four banks during refresh cycles:
	00: 0 SDRAM clocks
	01: 1 SDRAM clocks (Default)
	10: 2 SDRAM clocks
	11: 4 SDRAM clocks
	Staggering is used to help reduce power spikes during refresh by refreshing one bank at a time. If only one bank is installed,
	this field must be written as 00.

5	2CLKADDR (Two Clock Address Setup). Assert memory address for one extra clock before CS# is asserted.
	0: Disable.
	1: Enable.
	This can be used to compensate for address setup at high frequencies and/or high loads.


18		AMD Geode™ SC1200/SC1201 Processor Data Book

Image 18

AMD SC1200/SC1201 Processor Memory Controller Register Summary, SC1200/SC1201 Processor Memory Controller Registers

Contents

Publication ID 32579B AMD Geode SC1200/SC1201 Processor Data Book Advanced Micro Devices, Inc. All rights reserved Contacts Trademarks Contents Core Logic Module Electrical SpecificationsPackage Specifications Video Processor Module Typical Battery Current Normal Operation Mode Power Supply ConnectionsTypical Battery Configuration ACCESS.bus Data Transaction USB EOP Width Timing Diagram 420 Multiword DMA Data Transfer Timing Diagram 405USB Data Signal Rise and Fall Timing Diagram 419 Fast IR Timing MIR and FIR Diagram 422 426 424425 427 32579B ACB1 and ACB2 Configuration Register IRCP/SP3 Configuration RegisterSerial Ports 1 and 2 Configuration Register Parallel Port Configuration Register 166 Banks 0 and 1 Common Control and Status Registers 118119 167 F2BAR4+I/O Offset IDE Controller Configuration Registers Pciusb USB PCI Configuration Register SummaryF0BAR0+I/O Offset Gpio Configuration Registers F3 PCI Header Registers for Audio Configuration 402 384400 404 Core Logic General DescriptionVideo Processor SuperI/O GX1 Processor Module FeaturesGeneral Features Video Processor Module Nand Eeprom Other FeaturesCore Logic Module SuperI/O Module 32579B GX1 Module Memory ControllerArchitecture Overview 32579B Width Memory Offset Bits Type Name/Function Reset Value SC1200/SC1201 Processor Memory Controller Register SummarySC1200/SC1201 Processor Memory Controller Registers MCMEMCNTRL2 R/W Rsvd Reserved. Write as 0070h Bit Description GXBASE+8408h-840BhMcbankcfg R/W Rsvd Reserved. Write as GXBASE+840Ch-840Fh Mcgbaseadd R/W Mcdradd R/WMcdracc R/W 1 GX1 Module Interface Fast-PCI BusDisplay Video Input Port Power-On Reset Clock, Timers, and Reset LogicReset Logic System Reset 32579B SC1200/SC1201 Signal Definitions 32579BAMD Geode Processor USB Jtag Interface Signal Definitions Legend Mnemonic Definition SC1200/SC1201 Configuration BGU481 Ball Assignment Sorted by Ball Number REQ0# GNT0# GPIO7 AFD#/DSTRB# PAR GPIO12 FTRDY# AC1 IDEDATA1 Buffer1 Power Signal Name Ball Buffer Power Signal Name BGU481 Ball Assignment Sorted Alphabetically by Signal Name Signal Name Ball No C11 F30FC/BE0# D21 FC/BE1# B17 MD25 AC28 MD23MD24 MD26 AC29 A2, A30, B2, B13 C24N13, N14, N18 F31 Nominal External PU/PD Strap Settings Strap OptionsStrap Options Default Alternate Ball No Signal Configuration Multiplexing ConfigurationTwo-Signal/Group Multiplexing TFT, CRT, PCI, GPIO, System ACCESS.bus Internal TestAC97 Fpci Monitoring Three-Signal/Group Multiplexing Four-Signal/Group Multiplexing Gpio UART2 IDE2 Maximum Core Clock Multiplier. These strap signals Signal DescriptionsSignal Name Ball No Type Description Mux Boot ROM is 16 Bits Wide. This strap signal enables Memory Interface Signals Column Address Strobe. RAS#, CAS#, WE# and CKE Video Port Interface Signals 4 CRT/TFT Interface Signals Digital RGB Data to TFT TV Interface Signals Super Video Chrominance. S-Video chrominance sigCurrent Compensation for TV DAC. a 0.1 µF to 1.2 µF ACCESS.bus Interface Signals PCI Bus Interface Signals INTC# INTA#INTB# INTD# AA2 DEVSEL# STOP#LOCK# BHE# REQ1# PERR#SERR# REQ0# Sub-ISA Interface Signals Low Pin Count LPC Bus Interface Signals IDE Interface Signals Universal Serial Bus USB Interface Signals Serial Ports UARTs Interface Signals Parallel Port Interface Signals Fast Infrared IR Port Interface Signals General Purpose Wakeup I/Os. These signals each 15 AC97 Audio Interface SignalsPower Management Interface Signals Serial Bus Synchronization. This bit is asserted to syn PWRCNT1 AK6 Suspend Power Plane Control 1 and 2. Control signalPWRBTN# AH5 PWRCNT2 AL7 Gpio Interface Signals Fast-PCI Bus Monitoring Signals. When enabled, this Debug Monitoring Interface SignalsJtag Interface Signals System Management Interrupt. This is the input to Memory Internal Test Signals. These signals are used Test and Measurement Interface SignalsPLL6, PLL5 and PLL2 Bypass. These signals are used Thermal Diode Positive / Negative. These signals are for Power and Ground Connections1 General Configuration Block 32579B Configuration Block AddressesGeneral Configuration Block Register Summary Width Offset Bits PMR27 Ball # Internal Test Signals Name Add’l DependenciesOther Signal Add’l Dependencies Fpcimon General Configuration Block Ball # IDE Signals CRT, Gpio and TFT Signals Name PP/ACB1/FPCI TFT/VOP Name Add’l Dependencies Ball # Gpio Signals LPC Signals Name Add’l Dependencies 32579BGeneral Configuration Block Reserved General Configuration Block Offset 3Eh-3Fh Configuration Base Address Register CBA RO Offset 38h Interrupt Selection Register Intsel R/WOffset 3Dh Revision Register REV RO Watchdog Timer Functional Description 3describes the Watchdog registers Watchdog RegistersWatchdog Interrupt Usage Hints Watchdog Status Register Wdsts R/WC Reset Value 00h High-Resolution TimerHigh-Resolution Timer Registers Offset 05h-07h Tmen Timer Interrupt Enable Reset Value xxxxxxxxhTmclksel Timer Clock Select Bit Description Offset 08h-0Bh Clock Generators and PLLs 1 27 MHz Crystal Oscillator Crystal Oscillator Circuit ComponentsComponent Parameters Values Tolerance Core Clock Frequency 2 GX1 Module Core ClockInternal Fast-PCI Clock Strapped Core Clock Frequency SuperI/O Clocks Core Logic Module ClocksVideo Processor Clocks Clock Generator Configuration Clock RegistersClock generator and PLL registers are described in Table 33.3 MHz 1514Reserved. Must be set to 1110 66.7 MHz Outstanding Features ISAAB1C AB1D AB2C AB2D Serial Port PC98 and Acpi CompliantParallel Port Serial Port 3 / Infrared IR Communication Port Internal Internal Signals AccessSignals Module Architecture Index-Data Register Pair Configuration Structure / AccessSIO Configuration Options LDN Assignments Default Configuration Setup Address Decoding Logical Device Control and Configuration Registers Standard Configuration RegistersSIO Control and Configuration Registers Standard Logical Device Configuration Registers Standard Configuration Registers Index F0h-FEh Logical Device Configuration R/W 32579BSuperI/O ModuleDMA Channel Select 1 R/W Index Type Name Power Rail Reset Value SIO Control and Configuration RegistersSIO Control and Configuration Register Map SID. SIO ID Logical Device Control and Configuration Relevant RTC Configuration Registers RTC Configuration Registers Relevant SWC Registers LDN 01h System Wakeup ControlBase Address MSB register 10. IRCP/SP3 Configuration Register Relevant IRCP/SP3 Registers 11. Relevant Serial Ports 1 and 2 Registers 12. Serial Ports 1 and 2 Configuration RegisterSerial Ports 1 and 2 Configuration register LDN 03h and 08h Serial Ports 1 ACB1 and ACB2 Configuration register 14. ACB1 and ACB2 Configuration RegisterLDN 05h and 06h ACCESS.bus Ports 1 13. Relevant ACB1 and ACB2 Registers 16. Parallel Port Configuration Register 15. Relevant Parallel Port Registers Bus Interface RTC Clock Generation X32I External X32O Battery = 0.1 μFReal-Time Clock RTC 17. Crystal Oscillator Circuit Components Oscillator Startup Signal ParametersExternal Elements External Oscillator Daylight Saving AlarmsTimekeeping Data Format Leap Years Power Supply 18. System Power States Battery-Backed RAMs and Registers Interrupt Handling110 20. RTC Registers RTC Registers19. RTC Register Map Index Type Name CRD is Index 05h Hours Alarm Register Hora R/WIndex 04h Hours Register HOR R/W 112 Index Programmable Century Register CEN R/W Index Programmable Month Alarm Register Mona R/WIndex 0Ch RTC Control Register C CRC RO AMD Geode SC1200/SC1201 Processor Data Book 113 23. BCD and Binary Formats 21. Divider Chain Control / Test Selection22. Periodic Interrupt Rate Encoding Parameter BCD Format Binary Format RTC General-Purpose RAM Map 24. Standard RAM Map 0Eh 7Fh Battery-backed general-purpose Byte RAM00h 7Fh Battery-backed general-purpose Byte RAM 25. Extended RAM Map System Wakeup Control SWC Event Detection26. Time Range Limits for Ceir Protocols Type Name Value SWC Registers27. Banks 0 and 1 Common Control and Status Register Map Offset Type Name Value 29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Ceir Pulse Change, Range 1, High Limit Bit Description Ceir Wakeup Range 1 RegistersBank 1, Offset 0Ah IRWTR1L Register R/W Ceir Wakeup Range 2 Registers ABD ABC ACCESS.bus InterfaceData Transactions AMD Geode SC1200/SC1201 Processor Data Book 121 Acknowledge ACK Cycle ABD MSBABC ACK Arbitration on the Bus Master ModeAcknowledge After Every Byte Rule Addressing Transfer Formats Master Receive Sending the Address ByteMaster Transmit Master Stop Slave Mode Configuration ACB Registers 31. ACB Register Map32. ACB Registers MASTER. RO EN Enable Reserved Inten Interrupt EnableSaen Slave Address Enable Stop Stop 33. Parallel Port Register Map for First Level Offset Legacy Functional BlocksParallel Port 34. Parallel Port Register Map for Second Level Offset 35. Parallel Port Bit Map for First Level Offset 36. Parallel Port Bit Map for Second Level Offset130 Uart Functionality SP1 and SP2 Type Name 40. Bank 2 Register Map 38. Bank Selection Encoding39. Bank 1 Register Map 41. Bank 3 Register Map Register Bits 42. Bank 0 Bit Map43. Bank 1 Bit Map Register Bits Offset 44. Bank 2 Bit Map 45. Bank 3 Bit Map134 IRCP/SP3 Register and Bit Maps 3.1 IR/SP3 Mode Register Bank Overview46. Bank 0 Register Map 01h Register Throughout Offset 00h All Banks 49. Bank 2 Register Map 47. Bank Selection Encoding48. Bank 1 Register Map BSR Bits Bank Selected Functionality 50. Bank 3 Register Map 51. Bank 4 Register Map52. Bank 5 Register Map 53. Bank 6 Register Map 54. Bank 7 Register Map55. Bank 0 Bit Map 58. Bank 3 Bit Map 56. Bank 1 Bit Map57. Bank 2 Bit Map 59. Bank 4 Bit Map 60. Bank 5 Bit Map 61. Bank 6 Bit Map62. Bank 7 Bit Map Feature List Video Processor Interface ConfigIntegrated Audio Low Pin Count LPC Interface Fast-PCI Interface to External PCI Bus Pserial Interface IDE Controller IDE Configuration RegistersPIO Mode Video Retrace Interrupt Physical Region Descriptor Format Stop UltraDMA/33 Signal DefinitionsUltraDMA/33 Mode DMARDY# Strobe Ideiordy IOCS0#/IOCS1# Universal Serial BusSub-ISA Bus Interface Docw Fast-PCICLK Sub-ISA Support of Delayed PCI TransactionsSub-ISA Bus Cycles AD310 Read AD310 Write FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# 5.4 I/O Recovery DelaysREQ# GNT# Sub-ISA Bus Data Steering ISA DMA SD150AD310 ROM Interface PCI and Sub-ISA Signal Cycle MultiplexingCycle Multiplexed PCI / Sub-ISA Balls PCI DMA Controller FRAME# TRDY#, IRDY#ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP# DMA Channels DMA Transfer Types DMA Transfer ModesDMA Controller Registers DMA Priority DMA Page Registers and Extended Addressing Programmable Interval TimerDMA Addressing Capability DMA Address Generation Master PIC Interrupt MappingProgrammable Interrupt Controller Mapping PIC Shadow Register PIC Interrupt SequencePIC I/O Registers PCI Compatible Interrupts 7.1 I/O Port 092h System Control Fast Keyboard Gate Address 20 and CPU ResetKeyboard Support 7.2 I/O Port 061h System Control Power Management Logic Wakeup Events Capability Power Planes Control Signals vs Sleep States Power Planes vs. Sleep/Global StatesPower Management Events Thermal Monitoring Power ButtonPower Button Override AMD Geode SC1200/SC1201 Processor Data Book 161 APM Support Power Management ProgrammingCPU Power Management Suspend Modulation Volt Suspend Save-to-DiskAMD Geode SC1200/SC1201 Processor Data Book 163 General Purpose Timers Peripheral Power ManagementDevice Idle Timers and Traps Acpi Timer Register Power Management SMI Status Reporting Registers ModuleF1BAR0+I/O Located at F0 Index xxh Unless Otherwise Noted Device Power Management Programming SummaryPower Management Programming Summary F1BAR0+I/O Gpio Interface Integrated Audio Audio Data Buffer Reserved Size 11. Physical Region Descriptor FormatByte Memory Region Base Address PRD1 PRD2 PRD3 12.2 AC97 Codec Interface Codec Configuration/Control RegistersCodec Command Register Codec Gpio Status and Control Registers VSA Technology Trap SMI Enable RegisterVSA Technology Support Hardware Audio SMI Related Registers Module Core Logic Module Internal IRQ Control Register IRQ Configuration RegistersInternal IRQ Enable Register LPC Interface 12. Cycle Types PCI Configuration Space and Access Methods 13. PCI Configuration Address Register 0CF8hRegister Descriptions Core Logic module. Included in the tables are the regis Ter’s reset values and page references where the bit forRegister Summary Mats are found Width Reset Reference F0 Index Bits AMD Geode SC1200/SC1201 Processor Data Book 177 32579BCore Logic Module Register Summary 178 F0BAR0+ 15. F0BAR0 Gpio Support Registers Summary16. F0BAR1 LPC Support Registers Summary F0BAR1+ 18. F1BAR0 SMI Status Registers Summary F1BAR0+ 00h-03h Pcnt Processor Control Register 19. F1BAR1 Acpi Support Registers SummaryF1BAR1+ 20h PM2CNT PM2 Control Register 00h 21h-FFh Not Used Width Reset Reference F2 Index Bits 182 22. F3 PCI Header Registers for Audio Support Summary Width Reset Reference F3 Index Bits21. F2BAR4 IDE Controller Support Registers Summary F2BAR4+ F3BAR0+ Width Reset23. F3BAR0 Audio Support Registers Summary 184 F5BAR0+ Width Reset Reference F5 Index Bits25. F5BAR0 I/O Control Support Registers Summary AMD Geode SC1200/SC1201 Processor Data Book 185 Pciusb 26. Pciusb USB PCI Configuration Register SummaryName Reset Value Width Reference Index Bits 27. Usbbar USB Controller Registers Summary USBBAR0AMD Geode SC1200/SC1201 Processor Data Book 187 28. ISA Legacy I/O Register Summary DMA Page Registers Table188 Programmable Interrupt Controller Registers Table Programmable Interval Timer Registers TablePort Type Name Reference Keyboard Controller Registers Table Chipset Register Space Bridge, GPIO, and LPC Registers FunctionGeneral Remarks Index 09h-0Bh Core Logic Module Bridge, GPIO, and LPC Registers FunctionData Parity Detected. This bit is set when AMD Geode SC1200/SC1201 Processor Data Book 191 Index 0Fh PCI Bist Register RO Index 0Eh PCI Header Type RO Reset Value 80hSlave response 316 Gpio Base Address PCI Subtractive Decode AMD Geode SC1200/SC1201 Processor Data Book 193 Index 43h Reset Control Register R/W Reset Value 01hIndex 42h 194 Index 47h Index 45hIndex 46h AMD Geode SC1200/SC1201 Processor Data Book 195 PIT Counter 1 Enable Reset Value 7BhPIT Software Reset PIT Counter 0 Enable ROM/AT Logic Control Register R/W Reset Value 98h Generate SMI on A20M# ToggleAMD Geode SC1200/SC1201 Processor Data Book 197 Index 5Bh Decode Control Register 2 R/W Bit Description Index 54h-59hIndex 5Ah 198 INTD# Ball AA2 Target Interrupt INTB# Ball C26 Target InterruptINTA# Ball D26 Target Interrupt INTC# Ball C9 Target Interrupt 150 Index 72h200 Index 76h Index 73hIndex 74h-75h Chip Select 0 Positive Decode IOCS0# Ing the upper 19 bits of the incoming PCI address AD3113 202 Power Management Enable Register 2 R/W Reset Value 00h Timer expires Disable EnableAMD Geode SC1200/SC1201 Processor Data Book 203 204 Parallel/Serial Access Trap Power Management Enable Register 3 R/W Reset Value 00hKeyboard/Mouse Access Trap AMD Geode SC1200/SC1201 Processor Data Book 205 Index 83h Power Management Enable Register 4 R/W Floppy Disk Access TrapPrimary Hard Disk Access Trap 206 Index 84h Second Level PME/SMI Status Mirror Register 1 RO AMD Geode SC1200/SC1201 Processor Data Book 207 208 AMD Geode SC1200/SC1201 Processor Data Book 209 Index 88h General Purpose Timer 1 Count Register R/W Reserved. Always reads210 Re-trigger General Purpose Timer 1 on Floppy Disk Activity Second MillisecondAMD Geode SC1200/SC1201 Processor Data Book 211 Index 8Bh General Purpose Timer 2 Control Register R/W Index 8Dh Video Speedup Timer Count Register R/W212 Index 8Fh-92h Index 93hAMD Geode SC1200/SC1201 Processor Data Book 213 Index 98h-99h Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/WIndex 97h 214 Index A6h-A7h Video Idle Timer Count Register R/W Index A8h-A9h Video Overflow Count Register R/W Index B0h-B3h Index AEh CPU Suspend Command Register WOIndex AFh Suspend Notebook Command Register WO Index B4h Index B9h PIC Shadow Register RO Index BAh PIT Shadow Register ROAMD Geode SC1200/SC1201 Processor Data Book 217 Index BDh-BFh Index BCh Clock Stop Control Register R/W Reset Value 00hReserved. Set to CPU Clock Stop Index C0h-C3h Index CDh Bit Description Index CChMask Index CEh Index F5h Second Level PME/SMI Status Register 2 RC Index EDh-F3hIndex F4h 220 Index F6h Second Level PME/SMI Status Register 3 RC AMD Geode SC1200/SC1201 Processor Data Book 221 Index F7h Second Level PME/SMI Status Register 4 RC Reserved. Read as222 Index F8h-FFh Gpio Support Registers 30. F0BAR0+I/O Offset Gpio Configuration RegistersI/O mapped registers accessed through F0BAR0 Ration registers are located. -29gives the bit formats 316 Reserved. Must be set to Offset 14h-17h GPDI1 Gpio Data In 1 Register ROF0BAR0+I/O Offset 18h is set, this edge generates a PME AMD Geode SC1200/SC1201 Processor Data Book 225 010011 = GPIO19 ball C9 000100 Bank010010 = GPIO18 ball AG1 000011 010100 = GPIO20 balls A9, N31 000101 AMD Geode SC1200/SC1201 Processor Data Book 227 3121 31. F0BAR1+I/O Offset LPC Interface Configuration RegistersLPC Support Registers Reserved. Set to AMD Geode SC1200/SC1201 Processor Data Book 229 Polarity selection 230 Number of IRQ Data Frames Reserved Serial IRQ EnableSerial IRQ Interface Mode AMD Geode SC1200/SC1201 Processor Data Book 231 232 LPC Floppy Disk Controller Address Select. Selects I/O Port LPC Game Port 1 Address Select. Selects I/O PortLPC Game Port 0 Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port 234 Bit SMI Status and Acpi Registers Function 32. F1 PCI Header Registers for SMI Status and Acpi Support Core Logic Module SMI Status and Acpi Registers Function 33. F1BAR0+I/O Offset SMI Status RegistersSMI Status Support Registers AMD Geode SC1200/SC1201 Processor Data Book 237 Suspend Modulation Enable Mirror. Read to Clear Offset 02h-03h Top Level PME/SMI Status Register RO/RC238 AMD Geode SC1200/SC1201 Processor Data Book 239 Offset 04h-05h Yes To enable SMI generation, set F0 Index 82h6 =Yes To enable SMI generation, set F0 Index 82h5 = 240 AMD Geode SC1200/SC1201 Processor Data Book 241 Offset 0Ah-1Bh These addresses should not be written Offset 1Ch-1Fh242 Offset 24h-27h External SMI Register R/W 3124AMD Geode SC1200/SC1201 Processor Data Book 243 244 AMD Geode SC1200/SC1201 Processor Data Book 245 Offset 28h-4Fh Not Used Reset Value 00h 50h-FFh246 Acpi Support Registers Offset 06h Smicmd OS/BIOS Requests Register R/W34. F1BAR1+I/O Offset Acpi Support Registers Clkval Clock Throttling Value. CPU duty cycle SCI generation is always enabled 248 Offset 0Ch-0Dh PM1ACNT PM1A Control Register R/W Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W1511 1514 Reserved. Must be set to 250 AMD Geode SC1200/SC1201 Processor Data Book 251 252 Consumer Electronic Infrared Gpwio Control Register 1 R/W Reset Value 00hGpwio Control Register 2 R/W Reset Value 00h Reserved 02h0 Gpwio Data Register R/W Reset Value 00h Reserved Reset Value 00h 254 Offset 21h-FFh Reset Value 00000F00hBit Description Offset 18h-1Bh AMD Geode SC1200/SC1201 Processor Data Book 255 IDE Controller Registers Function Bit Description Index 30h-3Fh PIOMODE. PIO modeCore Logic Module IDE Controller Registers Function AMD Geode SC1200/SC1201 Processor Data Book 257 258 Index 58h-5Bh Bit Description Index 48h-4BhIndex 50h-53h Index 60h-FFh IDE Controller Support Registers 260 Offset 0Bh Offset 09hOffset 0Ah Offset 0Ch-0Fh 37. F3 PCI Header Registers for Audio Configuration Audio Registers Function Core Logic Module Audio Registers Function 38. F3BAR0+Memory Offset Audio Configuration RegistersAudio Support Registers Offset 04h-07h 264 AMD Geode SC1200/SC1201 Processor Data Book 265 These bits change only on a fast write to an even address 2316266 AMD Geode SC1200/SC1201 Processor Data Book 267 268 Mask Internal IRQ11. Write Only Mask Internal IRQ15. Write OnlyMask Internal IRQ14. Write Only Mask Internal IRQ10. Write Only Assert Masked Internal IRQ14 Mask Internal IRQ4. Write OnlyMask Internal IRQ3. Write Only Reserved. Set to Assert Masked Internal IRQ12 Bit Description Assert Masked Internal IRQ1 AMD Geode SC1200/SC1201 Processor Data Book 271 Offset 2Ah-2Bh Audio Bus Master 1 Command Register R/W Reset Value 00hOffset 29h Audio Bus Master 1 SMI Status Register RC Offset 2Ch-2Fh Offset 32h-33h Audio Bus Master 2 Command Register R/W Reset Value 00hOffset 31h Audio Bus Master 2 SMI Status Register RC Offset 34h-37h Offset 3Ah-3Bh Audio Bus Master 3 Command Register R/W Reset Value 00hOffset 39h Audio Bus Master 3 SMI Status Register RC Offset 3Ch-3Fh Offset 42h-43h Audio Bus Master 4 Command Register R/W Reset Value 00hOffset 41h Audio Bus Master 4 SMI Status Register RC Offset 44h-47h Offset 4Ah-4Bh Audio Bus Master 5 Command Register R/W Reset Value 00hOffset 49h Audio Bus Master 5 SMI Status Register RC Offset 4Ch-4Fh Bus Expansion Interface Function 39. F5 PCI Header Registers for X-Bus Expansion Index 24h-27h Bit Description Index 1Ch-1FhIndex 20h-23h Index 28h-2Bh Index 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 58h F5BARx Initialized Register R/W Reset Value 00hIndex 48h-4Bh F5BAR2 Mask Address Register R/W Index 50h-53h F5BAR4 Mask Address Register R/W Bit Description Index 64h-67h Index 68h-FFh280 40. F5BAR0+I/O Offset X-Bus Expansion Registers Bus Expansion Support RegistersF5 Index 10h, Base Address Register 0 F5BAR0 set Iotestporten Debug Test Port Enable Three USB transceivers. Default = 128USB transceivers. Default = 282 Core Logic Module USB Controller Registers Pciusb 41. Pciusb USB PCI Configuration RegistersUSB Controller Registers Pciusb AMD Geode SC1200/SC1201 Processor Data Book 283 Bit Description Index 06h-07h Status Register R/W Reset Value 08hIndex 0Dh Latency Timer Register R/W Reserved. Must be set to Index 08h 42. USBBAR+Memory Offset USB Controller Registers 32579BCore Logic Module USB Controller Registers Pciusb 286 RootHubStatusChangeEnable HcInterruptEnable Register R/W Reset Value = 00000000hOwnershipChangeEnable FrameNumberOverflowEnable Offset 24h-27h Bit Description StartOfFrameEnableOffset 20h-23h Offset 28h-2Bh Bit Description Offset 38h-3Bh HcFrameRemaining Register RO Reset Value = 00000628hReset Value = 01000003h Reserved. Read 0s Offset 50h-53h HcRhStatus Register R/W BalPowerRead LocalPowerStatusChange. Not supported. Always read 3018 Read PortSuspendStatus HcRhPortStatus1 Register R/W Reset Value = 00000000hRead PortResetStatus AMD Geode SC1200/SC1201 Processor Data Book 291 Read PortEnableStatus Read CurrentConnectStatus292 AMD Geode SC1200/SC1201 Processor Data Book 293 Reserved Reset Value = xxh 294 AMD Geode SC1200/SC1201 Processor Data Book 295 ISA Legacy Register Space 43. DMA Channel Control Registers Core Logic Module ISA Legacy Register Space Priority ModeTiming Mode Write 32579BCore Logic Module ISA Legacy Register Space Transfer ModeChannel Number Mode Select Bit Description Port 00Bh Write DMA Command Register, Channels UndefinedAMD Geode SC1200/SC1201 Processor Data Book 299 Port 0D6h Bit Description Port 0D2hPort 0D4h Port 0D8h 44. DMA Page Registers 45. Programmable Interval Timer Registers Counter Value Read Current Counter Mode BCD ModeBit Description Port 042h Write Port 043h R/W 46. Programmable Interrupt Controller Registers Bit Description IRQ1 / IRQ9 Mask Poll CommandRegister Read Mode IRQ0 / IRQ8 Mask IRQ5 / IRQ13 In-Service Interrupt Service Register IRQ7 / IRQ15 In-ServiceIRQ6 / IRQ14 In-Service IRQ4 / IRQ12 In-Service 47. Keyboard Controller Registers 48. Real-Time Clock Registers 49. Miscellaneous Registers AMD Geode SC1200/SC1201 Processor Data Book 309 310 Hardware Video Acceleration General FeaturesVideo Input Port VIP Interface Graphics-Video Overlay and Blending VIP Display ModesVideo Input Port Tvout VBI Support Functional DescriptionVideo Support Video Processor Module Active Video Video Input Port VIP Direct Mode and Capture Mode Configurations Bob Address not changed during runtimeAMD Geode SC1200/SC1201 Processor Data Book 317 Weave Capture VBI Mode Ping-pongs between the two buffers during runtimeAMD Geode SC1200/SC1201 Processor Data Book 319 Line Buffer Video BlockVideo Input Formatter 320 Horizontal Downscaler Horizontal Downscaler with 4-Tap FilteringFiltering Maintaining Aspect Ratio 2.5 2-Tap Vertical and Horizontal Upscalers Line BuffersFormatter Ai,j Ai,j+1 Ai+1,jAi+1,j+1 RGB Mixer/Blender BlockCSC RAM Flicker Valid Mixing/Blending ConfigurationsFilter2 Bit Mode Comment 324 RGB to YUV CSC YUV to RGB CSC in Video Data PathGamma Correction 3.4 1/2 Y Flicker Filter Cursor Window Graphics WindowVideo Window Alpha Windows Color Truth Table for Alpha BlendingMixing/Blending Operation CHROMASEL1 328 Flicker Filter and Scan Rate Conversion Flicker Filter, Interlaced Video YUV Mixing/Blending ModeTvout Block Vesa Vesa DDSC2B and Dpms Support Integrated DACs HSYNC, VSYNC, TFTDE, Tftdck Power SequenceTFT Interface T1 is a programmable multiple of frame time T0+T1 Compare Pump Filter Divider Out Divider Phase Charge LoopIntegrated PLL 332 F4BAR0 Video Processor Configuration Registers Summary F4 PCI Header Registers for Video Processor Support SummaryF4BAR0+ 32579BVideo Processor Module Register Summary 334 Encoder Registers Name Value Tvout Configuration RegistersF4BAR2 VIP Support Registers Summary F4BAR2+ Video Processor Registers Function Reset Value 0504hReset Value 030000h 3112 VIP Base Address 110 Address Range. Read Only Video Processor Module Video Processor Registers Function Index 3Eh-FFh ReservedAMD Geode SC1200/SC1201 Processor Data Book 337 Video Processor Support Registers F4BAR0 Video Configuration Register R/W Reset Value 00000000hEN42X Enable 42x Format. Allows format selection To 0 or 1 should be written with a value that is read 3028 Offset 04h-07h Display Configuration Register R/WTions of the power sequence control lines 1614 Ddcsdaout DDC Output Data. DDC data bit for output Offset 08h-0Bh Video X Position Register R/W 340 Bit Description 100 AMD Geode SC1200/SC1201 Processor Data Book 341 Bit Description Offset 1Ch-1Fh Reset Value 00001400h12 PLL2PWREN PLL2 Power-Down Enable Block Offset 20h-23h FLTCO4 Filter Coefficient 4. For the tap-4 filter DTS Downscale Type SelectOffset 40h-43h Video Downscaler Coefficient Register R/W FLTCO3 Filter Coefficient 3. For the tap-3 filter Reset Value 00060000h Reserved Signen Signature EnableReset Value 0000xxxxh Bit Description Offset 44h-47h CRC Signature Register R/W 100 i.e., shift one line otherwise, leave at AMD Geode SC1200/SC1201 Processor Data Book 345 Offset 60h-63h Alpha Window 1 X Position Register R/W Bit Description Offset 50h-53hOffset 54h-57h 346 3118 Decremented until it is reloaded via bit 17 LoadalphaAMD Geode SC1200/SC1201 Processor Data Book 347 348 Offset 400h-403h Offset 90h-93hOffset 94h-97h Video Fifo Underflow Empty VBI Fifo Overflow Full Video Fifo OverFlow FullVBI Fifo Underflow Empty Upscale horizontally VBI data by 3120 Reserved 190 Genlocktouten GenLock Timeout EnableBit Description Offset 414h-417h Port Offset 41Ch-41Fh Offset 424h-427h Ctgenlocken Enable Continuous GenLock FunctionSggenlocken Enable a Single GenLock Function 3121 Reserved 200 Bit Description Offset 80Ch-80Fh Offset 810h-813h Offset 81Ch-81Fh Horintp Horizontal InterpolationFieldinvr Field Invert Offset C00h-C03h 2920 AMD Geode SC1200/SC1201 Processor Data Book 355 Offset C08h-C0Bh TV DAC Mode Bits Ball NoA23 Mode D24 A24 Offset C28h-C2Bh Offset C24h-C27h3114 AMD Geode SC1200/SC1201 Processor Data Book 357 Bit Description Offset C2Ch-C2Fh Reset Value 00000020hReset Value 00000004h Offset C50h-C53h All other decodes Reserved 10. F4BAR2+Memory Offset VIP Configuration RegistersVIP Support Registers F4BAR2 AMD Geode SC1200/SC1201 Processor Data Book 359 Reserved.Read Only Current Field. Read Only Capture Store to Memory VBI DataCapture Store to Memory Video Data 2322 Offset 14h-17h Video Data Capture Active. Read OnlyReserved. Read Only Run Status. Read Only Offset 24h-27h Video Data Even Base Register R/W Offset 44h-47h VBI Data Even Base Register R/W 3116 Reserved 150Offset 2Ch-3Fh Offset 48h-4Bh VBI Data Pitch Register R/W Mandatory Instruction Support Jtag Mode Instruction SupportTestability Jtag Optional Instruction Support 364 Electro Static Discharge ESD General SpecificationsPower/Ground Connections and Decoupling Absolute Maximum Ratings Symbol Parameter Min Typ Max Unit Comments Operating Conditions366 Power State Parameter Definitions Power Planes of External Interface SignalsPower Plane Signal Names VCC Balls VSS Balls DC Current DC Characteristics for On State Symbol Parameter Min Typ Max Unit Comment DC Characteristics for Active Idle, Sleep, and Off StatesSymbol Parameter Note Min Typ Max Unit Comments Ball Capacitance and Inductance VIO Pull-Up and Pull-Down ResistorsBalls with PU/PD Resistors External PU or PD resistor Wire DC CharacteristicsSymbol Description Reference 10. Buffer Types Inab DC Characteristics Inbtn DC CharacteristicsInpci DC Characteristics Ints DC Characteristics Instrp DC CharacteristicsINT DC Characteristics INTS1 DC Characteristics Inusb DC Characteristics ODn DC Characteristics Opci DC Characteristics Odpci DC CharacteristicsOp/n DC Characteristics Ousb DC Characteristics Symbol Parameter Value AC Characteristics11. Default Levels for Measurement Switching Parameters CLK Memory Controller Interface OutputsInputs SDCLK30, Sdclkout high time 32579BElectrical Specifications12. Memory Controller Timing Parameters 13.5 BA10, MD630 T1, t2, t3 t10SDCLK30 Control Output, MA120 MD630 Data Valid Read Data Vpckin Vref 14. Video Output Port Timing Parameters CRT and TFT Interface 15. TFT Timing Parameters Symbol Parameter Note Min Max Unit Comments 16. CRT Vesa Compatible DAC RED, GREEN, and Blue Outputs LSB DNL RESIRE LSB Tvref ACCESS.bus Interface 18. ACCESS.bus Input Timing Parameters19. ACCESS.bus Output Timing Parameters AB1D AB2D AB1C AB2C AB1D AB2D AB1C AB2C AB1D AB2D AB1CAMD Geode SC1200/SC1201 Processor Data Book 387 20. PCI AC Specifications PCI Bus 64VIO Equation a Equation B 21. PCI Clock Parameters Pciclk 0.4 V IO 22. PCI Timing Parameters Symbol Value Unit Comments 23. Measurement Condition ParametersMeasurement and Test Conditions Input Valid PowerSignals Ms typ 24. Sub-ISA Timing Parameters Symbol Parameter Bits Type CommentsSub-ISA Interface Bus Width Min Bus Width Min Max Symbol Parameter Bits Type Comments MEMR#/DOCR#/IOR# MEMR#/DOCR# ROMCS#/DOCCS#IOR#/RD#/TRDE# IOW#/WR# MEMW#/DOCW# IOW#/WR# MEMW#/DOCW# TRDE# DOCCS#/ROMCS#IOCS10# D150 LPC Interface 25. LPC and Serirq IDE Interface Timing 26. IDE General Timing Parameters IDE signals fall time from 0.9V IO to 0.1V IO = 40 pFIDE signals rise time from 0.1V IO to 0.9V IO = 40 pF IDERST# pulse width Cycle time min Mode Symbol Parameter Unit Comments27. IDE Register Transfer to/from Device Timing Parameters Width 8-bit min Read IDEDATA70 Addr valid1IDEIOR0# IDEIOW0# Write IDEDATA70 IDEIORDY0 2,3 28. IDE PIO Data Transfer to/from Device Timing Parameters 165 125 100402 IDEIOR0# IDEIOW0# Write IDEDATA150 Read IDEDATA150AMD Geode SC1200/SC1201 Processor Data Book 403 29. IDE Multiword DMA Data Transfer Timing Parameters IDECS10# IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0#AMD Geode SC1200/SC1201 Processor Data Book 405 Mode Symbol Parameter Min Max Unit Comments 30. IDE UltraDMA Data Burst Timing Parameters406 IDEIOR0# HDMARDY0# IDEREQ0STOP0 IDEIRDY0 DSTROBE0 IDEDATA150 at host IDEIRDY0 DSTROBE0 at deviceIDEDATA150 at device IDEIRDY0 DSTROBE0 at host 408 IDEIOR0#HDMARDY0# IDEDREQ0 device IDEDACK0# hostIDEIOW0#STOP0# host AMD Geode SC1200/SC1201 Processor Data Book 409 IDEDREQ0 device IDEIOW0# STOP0#410 IDECS01# IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# hostIDEIRDY0 DSTROBE0 device IDEDATA150 device IDEADDR20 IDEIORDY0 DDMARDY0 device DevicetUI IDEDACK0# hostIDEIOW0# STOP0# host IDEIOR0# HSTROBE0# host IDEDATA150 At host IDEIOR0# HSTROBE0# at device HSTROBE0#At host IDEDATA150 at device IDEIOR0# HSTROBE0# IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# hostIDEIORDY0# DDMARDY0# 414 IDEDACK0# host IDEIORDY0# DDMARDY0# deviceIDEDATA150 host IDEADDR20 IDECS01# AMD Geode SC1200/SC1201 Processor Data Book 415 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# host IDEDATA150 host IDECS01# IDEADDR20416 Universal Serial Bus USB 31. USB Timing Parameters Full Speed Receiver EOP Width NoteLow Speed Source Note Receiver data jitter tolerance for paired Source EOP widthHost upstream Low Speed Receiver EOP Width Note Differential Data Lines Crossover Points 2.0 Rise Time Fall TimeDifferential Data Lines Consecutive Transitions EOP Width Differential Data to SE0 SkewData Crossover Level Differential Crossover Points Data Lines SIR signal pulse width Modulation signal periodTCPN + Transmitter Sharp-IR and Consumer Remote Control Setting of the Rxhsc bit bit 5 of the Rccfg register Fast IR Port Timing 33. Fast IR Port Timing Parameters MIRFIR Busy ACK# STB# Symbol Parameter Min 35. Enhanced Parallel Port Timing ParametersUnit Comments AFD# 36. ECP Forward Mode Timing ParametersExtended Capabilities Port ECP Timing Busy 37. ECP Reverse Mode Timing Parameters BUSY# Sync inactive to Bitclk startup 162.8 Delay Audio Interface Timing AC97 38. AC Reset Timing ParametersAC97RST# inactive to Bitclk 162.8 Startup delay AC97RST# active low pulse width 40. AC97 Clocks Parameters AC97CLK Vold 41. AC97 I/O Timing Parameters SDATAOUT/SYNC SDATAIN, SDATAIN2 42. AC97 Signal Rise and Fall Timing Parameters Slot 43. AC97 Low Power Mode Timing ParametersEnd of Slot 2 to Bitclk Sdatain low Bitclk Sdataout 44. PWRBTN# Timing Parameters Power ManagementPower management event to ONCTL# Assertion ONCTL# PWRBTN# PWRBTN# ONTCL# PWRCNT21 POR# POR# 32KHZ 434 Jtag Interface 48. Jtag Timing Parameters TDI, TMS setup timeNon-test inputs setup time TDI, TMS hold time TDI TMS TDO Output SignalsInput Signals 436 Thermal Characteristics ΘJC ×C/WCase-to-Ambient Thermal Resistance Example @ 85C Assume P max = 5W and TA max = 40C Therefore Heatsink ConsiderationsExample Assume P max = 9W and TA max = 40C Therefore Physical Dimensions Package SpecificationsAMD Geode SC1200/SC1201 Processor Data Book 439 BGU481 Package Bottom View 440 Ordering Part Number Core Frequency Order InformationMacrovision Product Notice MHz Data Book Revision History Table A-1. Revision HistoryRevision # Revisions / Comments