AMD SC1200, SC1201 manual 252

32579B Core Logic Module - SMI Status and ACPI Registers - Function 1

Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)

Bit Description

5THRM_STS. Indicates if PME was caused by activity on THRM#.

0:No.

1:Yes.

Write 1 to clear.

For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[5] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1, (See Note 2 in the general description of this register above,)

4SMI_STS. Indicates if PME was caused by activity on the internal SMI# signal.

0:No.

1:Yes.

Write 1 to clear.

For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[4] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this register above.)

3GPIO_STS. Indicates if PME was caused by activity on any of the GPIOs (GPIO47-GPIO32 and GPIO15-GPIO0).

0:No.

1:Yes.

	Write 1 to clear.
	For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[3] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
	general description of this register above).
	F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME. In addition, the selected GPIO must be
	enabled as an input (F0BAR0+I/O Offset 20h and 24h).
2:1	Reserved. Reads as 0.

0PWR_U_REQ_STS. Indicates if PME was caused by a power-up request event from the SuperI/O module.

0:No.

1:Yes.

Write 1 to clear.

For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[0] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this register above.)

Offset 12h-13h GPE0_EN — General Purpose Event 0 Enable Register (R/W) Reset Value: 0000h

In order for the ACPI events described below to generate an SCI, the SCI_EN bit must also be set (F1BAR1+I/O Offset 0Ch[0] = 1).

The SCIs enabled in this register are globally enabled by setting F1BAR1+I/O Offset 0Ch[0] to 1. The status of the SCIs is reported in F1BAR1+I/O Offset 10h.

15:12 Reserved.

11Reserved.

10GPWIO2_EN. Allow GPWIO2 to generate an SCI.

0:Disable.

1:Enable.

A fixed high-to-low or low-to-high transition (debounce period) of 31 µs exists in order for GPWIO2 to be recognized. The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[6] to force an SMI.

9GPWIO1_EN. Allow GPWIO1 to generate an SCI.

0:Disable.

1:Enable.

See F1BAR1+I/O Offset 07h[3] for debounce information.

The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[5] to force an SMI.

8GPWIO0_EN. Allow GPWIO0 to generate an SCI.

0:Disable.

1:Enable.

See F1BAR1+I/O Offset 07h[3] for debounce information.

The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[4] to force an SMI.

252 AMD Geode™ SC1200/SC1201 Processor Data Book