AMD SC1200 manual Integrated PLL, Divider Phase Charge Loop, Compare Pump Filter Divider Out, 332

32579B Video Processor Module

7.2.8Integrated PLL

The integrated (CRT) PLL can generate frequencies up to 135 MHz from a single 27 MHz source. The clock fre- quency is programmable using two registers. Figure 7-16shows the block diagram of the Video Processor integrated PLL.

FREF is 27 MHz, generated by an external crystal and an integrated oscillator. FOUT is calculated from:

FOUT = (m + 1) / (n+ 1) x FREF

The integrated PLL can generate any frequency by writing into the CRT-m and CRT-n bit fields (FBAR0+Memory Off- set 2Ch). Additionally, 16 preprogrammed VGA frequencies can be selected via the PLL Clock Select register (F4BAR0+Memory Offset 2Ch[19:16]), if the crystal oscilla- tor has a frequency of 27 MHz. This PLL can be powered down via the Miscellaneous register (F4BAR0+Memory Offset 28h[12]).

FREF

n

Divider

Phase	Charge	Loop	VCO
Compare	Pump	Filter
m
Divider

Out

Divide

FOUT

Figure 7-16. PLL Block Diagram

332 AMD Geode™ SC1200/SC1201 Processor Data Book